mirror of https://github.com/KLayout/klayout.git
332 lines
8.8 KiB
Ruby
332 lines
8.8 KiB
Ruby
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# encoding: UTF-8
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# KLayout Layout Viewer
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# Copyright (C) 2006-2018 Matthias Koefferlein
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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if !$:.member?(File::dirname($0))
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$:.push(File::dirname($0))
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end
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load("test_prologue.rb")
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class DBNetlist_TestClass < TestBase
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def test_1_Resistors
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cls = RBA::DeviceClassResistor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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r1 = circuit.create_device(cls, "r1")
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r1.set_parameter(RBA::DeviceClassResistor::PARAM_R, 1.0)
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r2 = circuit.create_device(cls, "r2")
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r2.set_parameter("R", 3.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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r1.connect_terminal(RBA::DeviceClassResistor::TERMINAL_A, n1)
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n2 = circuit.create_net("n2")
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r1.connect_terminal(RBA::DeviceClassResistor::TERMINAL_B, n2)
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r2.connect_terminal(RBA::DeviceClassResistor::TERMINAL_A, n2)
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n3 = circuit.create_net("n3")
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r2.connect_terminal(RBA::DeviceClassResistor::TERMINAL_B, n3)
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circuit.connect_pin(pin_b, n3)
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n3):
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D r1 (A=n1,B=n2) [R=1]
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D r2 (A=n2,B=n3) [R=3]
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n3):
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D r1 (A=n1,B=n3) [R=4]
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END
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end
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def test_2_Capacitors
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cls = RBA::DeviceClassCapacitor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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c1 = circuit.create_device(cls, "c1")
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c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_C, 2.0)
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c2 = circuit.create_device(cls, "c2")
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c2.set_parameter("C", 3.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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c1.connect_terminal(RBA::DeviceClassCapacitor::TERMINAL_A, n1)
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n2 = circuit.create_net("n2")
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c1.connect_terminal(RBA::DeviceClassCapacitor::TERMINAL_B, n2)
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c2.connect_terminal(RBA::DeviceClassCapacitor::TERMINAL_A, n2)
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n3 = circuit.create_net("n3")
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c2.connect_terminal(RBA::DeviceClassCapacitor::TERMINAL_B, n3)
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circuit.connect_pin(pin_b, n3)
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n3):
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D c1 (A=n1,B=n2) [C=2]
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D c2 (A=n2,B=n3) [C=3]
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n3):
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D c1 (A=n1,B=n3) [C=1.2]
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END
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end
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def test_3_Inductors
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cls = RBA::DeviceClassInductor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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l1 = circuit.create_device(cls, "l1")
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l1.set_parameter(RBA::DeviceClassInductor::PARAM_L, 1.0)
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l2 = circuit.create_device(cls, "l2")
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l2.set_parameter("L", 3.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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l1.connect_terminal(RBA::DeviceClassInductor::TERMINAL_A, n1)
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n2 = circuit.create_net("n2")
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l1.connect_terminal(RBA::DeviceClassInductor::TERMINAL_B, n2)
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l2.connect_terminal(RBA::DeviceClassInductor::TERMINAL_A, n2)
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n3 = circuit.create_net("n3")
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l2.connect_terminal(RBA::DeviceClassInductor::TERMINAL_B, n3)
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circuit.connect_pin(pin_b, n3)
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n3):
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D l1 (A=n1,B=n2) [L=1]
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D l2 (A=n2,B=n3) [L=3]
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n3):
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D l1 (A=n1,B=n3) [L=4]
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END
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end
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def test_4_Diodes
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cls = RBA::DeviceClassDiode::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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d1 = circuit.create_device(cls, "d1")
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d1.set_parameter(RBA::DeviceClassDiode::PARAM_A, 1.0)
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d2 = circuit.create_device(cls, "d2")
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d2.set_parameter("A", 3.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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d1.connect_terminal(RBA::DeviceClassDiode::TERMINAL_A, n1)
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d2.connect_terminal(RBA::DeviceClassDiode::TERMINAL_A, n1)
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n2 = circuit.create_net("n2")
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d1.connect_terminal(RBA::DeviceClassDiode::TERMINAL_C, n2)
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d2.connect_terminal(RBA::DeviceClassDiode::TERMINAL_C, n2)
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circuit.connect_pin(pin_b, n2)
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n2):
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D d1 (A=n1,C=n2) [A=1]
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D d2 (A=n1,C=n2) [A=3]
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n2):
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D d1 (A=n1,C=n2) [A=4]
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END
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end
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def test_5_MOS3
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cls = RBA::DeviceClassMOS3Transistor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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d1 = circuit.create_device(cls, "d1")
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d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_L, 1.0)
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d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_W, 2.0)
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d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_AS, 3.0)
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d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_AD, 4.0)
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d2 = circuit.create_device(cls, "d2")
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d2.set_parameter("L", 1.0)
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d2.set_parameter("W", 3.0)
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d2.set_parameter("AS", 4.0)
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d2.set_parameter("AD", 5.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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pin_c = circuit.create_pin ("C")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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d1.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_S, n1)
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d2.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_S, n1)
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n2 = circuit.create_net("n2")
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circuit.connect_pin(pin_b, n2)
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d1.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_D, n2)
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d2.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_D, n2)
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n3 = circuit.create_net("n3")
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circuit.connect_pin(pin_c, n3)
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d1.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_G, n3)
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d2.connect_terminal(RBA::DeviceClassMOS3Transistor::TERMINAL_G, n3)
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n2,C=n3):
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D d1 (S=n1,G=n3,D=n2) [L=1,W=2,AS=3,AD=4]
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D d2 (S=n1,G=n3,D=n2) [L=1,W=3,AS=4,AD=5]
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n2,C=n3):
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D d1 (S=n1,G=n3,D=n2) [L=1,W=5,AS=7,AD=9]
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END
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end
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def test_6_MOS4
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cls = RBA::DeviceClassMOS4Transistor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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d1 = circuit.create_device(cls, "d1")
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d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_L, 1.0)
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d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_W, 2.0)
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d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_AS, 3.0)
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d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_AD, 4.0)
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d2 = circuit.create_device(cls, "d2")
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d2.set_parameter("L", 1.0)
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d2.set_parameter("W", 3.0)
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d2.set_parameter("AS", 4.0)
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d2.set_parameter("AD", 5.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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pin_c = circuit.create_pin ("C")
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pin_d = circuit.create_pin ("D")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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d1.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_S, n1)
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d2.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_S, n1)
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n2 = circuit.create_net("n2")
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circuit.connect_pin(pin_b, n2)
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d1.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_D, n2)
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d2.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_D, n2)
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n3 = circuit.create_net("n3")
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circuit.connect_pin(pin_c, n3)
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d1.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_G, n3)
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d2.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_G, n3)
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n4 = circuit.create_net("n4")
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circuit.connect_pin(pin_d, n4)
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d1.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_B, n4)
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d2.connect_terminal(RBA::DeviceClassMOS4Transistor::TERMINAL_B, n4)
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n2,C=n3,D=n4):
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D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=2,AS=3,AD=4]
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D d2 (S=n1,G=n3,D=n2,B=n4) [L=1,W=3,AS=4,AD=5]
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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Circuit (A=n1,B=n2,C=n3,D=n4):
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D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=5,AS=7,AD=9]
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END
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end
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end
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load("test_epilogue.rb")
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