2018-12-30 22:37:31 +01:00
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# encoding: UTF-8
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# KLayout Layout Viewer
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# Copyright (C) 2006-2018 Matthias Koefferlein
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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if !$:.member?(File::dirname($0))
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$:.push(File::dirname($0))
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end
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load("test_prologue.rb")
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class DBLayoutToNetlist_TestClass < TestBase
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def test_1_Basic
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ly = RBA::Layout::new
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ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l1.gds"))
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
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l2n.threads = 17
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l2n.max_vertex_count = 42
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l2n.area_ratio = 7.5
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assert_equal(l2n.threads, 17)
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assert_equal(l2n.max_vertex_count, 42)
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assert_equal(l2n.area_ratio, 7.5)
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r = l2n.make_layer(ly.layer(6, 0))
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assert_not_equal(l2n.internal_layout.object_id, ly.object_id)
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assert_equal(l2n.internal_layout.top_cell.name, ly.top_cell.name)
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assert_equal(l2n.internal_top_cell.name, ly.top_cell.name)
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assert_not_equal(l2n.layer_of(r), ly.layer(6, 0)) # would be a strange coincidence ...
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cm = l2n.const_cell_mapping_into(ly, ly.top_cell)
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(0 .. l2n.internal_layout.cells - 1).each do |ci|
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assert_equal(l2n.internal_layout.cell(ci).name, ly.cell(cm.cell_mapping(ci)).name)
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end
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ly2 = RBA::Layout::new
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ly2.create_cell(ly.top_cell.name)
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cm = l2n.cell_mapping_into(ly2, ly2.top_cell)
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assert_equal(ly2.cells, ly.cells)
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(0 .. l2n.internal_layout.cells - 1).each do |ci|
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assert_equal(l2n.internal_layout.cell(ci).name, ly2.cell(cm.cell_mapping(ci)).name)
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end
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end
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def test_2_ShapesFromNet
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ly = RBA::Layout::new
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ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l1.gds"))
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
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# only plain backend connectivity
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rmetal1 = l2n.make_polygon_layer( ly.layer(6, 0) )
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rmetal1_lbl = l2n.make_text_layer( ly.layer(6, 1) )
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rvia1 = l2n.make_polygon_layer( ly.layer(7, 0) )
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rmetal2 = l2n.make_polygon_layer( ly.layer(8, 0) )
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rmetal2_lbl = l2n.make_text_layer( ly.layer(8, 1) )
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# Intra-layer
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l2n.connect(rmetal1)
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l2n.connect(rvia1)
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l2n.connect(rmetal2)
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# Inter-layer
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l2n.connect(rmetal1, rvia1)
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l2n.connect(rvia1, rmetal2)
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l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
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l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
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# Perform netlist extraction
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l2n.extract_netlist
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assert_equal(l2n.netlist.to_s, <<END)
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Circuit TRANS ($1=$1,$2=$2):
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Circuit INV2 (OUT=OUT,$2=$2,$3=$3,$4=$4):
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XTRANS $1 ($1=$4,$2=OUT)
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XTRANS $2 ($1=$3,$2=OUT)
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XTRANS $3 ($1=$2,$2=$4)
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XTRANS $4 ($1=$2,$2=$3)
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Circuit RINGO ():
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XINV2 $1 (OUT=OSC,$2=FB,$3=VSS,$4=VDD)
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XINV2 $2 (OUT=$I29,$2=$I20,$3=VSS,$4=VDD)
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XINV2 $3 (OUT=$I28,$2=$I19,$3=VSS,$4=VDD)
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XINV2 $4 (OUT=$I30,$2=$I21,$3=VSS,$4=VDD)
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XINV2 $5 (OUT=$I31,$2=$I22,$3=VSS,$4=VDD)
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XINV2 $6 (OUT=$I32,$2=$I23,$3=VSS,$4=VDD)
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XINV2 $7 (OUT=$I33,$2=$I24,$3=VSS,$4=VDD)
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XINV2 $8 (OUT=$I34,$2=$I25,$3=VSS,$4=VDD)
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XINV2 $9 (OUT=$I35,$2=$I26,$3=VSS,$4=VDD)
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XINV2 $10 (OUT=$I36,$2=$I27,$3=VSS,$4=VDD)
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END
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assert_equal(l2n.probe_net(rmetal2, RBA::DPoint::new(0.0, 1.8)).inspect, "RINGO:FB")
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assert_equal(l2n.probe_net(rmetal2, RBA::DPoint::new(-2.0, 1.8)).inspect, "nil")
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n = l2n.probe_net(rmetal1, RBA::Point::new(2600, 1000))
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assert_equal(n.inspect, "RINGO:$I20")
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assert_equal(l2n.shapes_of_net(n, rmetal1, true).to_s, "(1660,-420;1660,2420;2020,2420;2020,-420);(1840,820;1840,1180;3220,1180;3220,820);(1660,2420;1660,3180;2020,3180;2020,2420);(1660,-380;1660,380;2020,380;2020,-380)")
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2019-01-04 17:41:09 +01:00
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shapes = RBA::Shapes::new
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l2n.shapes_of_net(n, rmetal1, true, shapes)
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r = RBA::Region::new
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shapes.each { |s| r.insert(s.polygon) }
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assert_equal(r.to_s, "(1660,-420;1660,2420;2020,2420;2020,-420);(1840,820;1840,1180;3220,1180;3220,820);(1660,2420;1660,3180;2020,3180;2020,2420);(1660,-380;1660,380;2020,380;2020,-380)")
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2018-12-30 22:37:31 +01:00
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end
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def test_10_LayoutToNetlistExtractionWithoutDevices
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ly = RBA::Layout::new
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ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l1.gds"))
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
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# only plain connectivity
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ractive = l2n.make_layer( ly.layer(2, 0) )
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rpoly = l2n.make_polygon_layer( ly.layer(3, 0) )
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rpoly_lbl = l2n.make_text_layer( ly.layer(3, 1) )
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rdiff_cont = l2n.make_polygon_layer( ly.layer(4, 0) )
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rpoly_cont = l2n.make_polygon_layer( ly.layer(5, 0) )
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rmetal1 = l2n.make_polygon_layer( ly.layer(6, 0) )
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rmetal1_lbl = l2n.make_text_layer( ly.layer(6, 1) )
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rvia1 = l2n.make_polygon_layer( ly.layer(7, 0) )
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rmetal2 = l2n.make_polygon_layer( ly.layer(8, 0) )
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rmetal2_lbl = l2n.make_text_layer( ly.layer(8, 1) )
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rsd = ractive - rpoly
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# Intra-layer
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l2n.connect(rsd)
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l2n.connect(rpoly)
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l2n.connect(rdiff_cont)
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l2n.connect(rpoly_cont)
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l2n.connect(rmetal1)
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l2n.connect(rvia1)
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l2n.connect(rmetal2)
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# Inter-layer
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l2n.connect(rsd, rdiff_cont)
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l2n.connect(rpoly, rpoly_cont)
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l2n.connect(rpoly_cont, rmetal1)
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l2n.connect(rdiff_cont, rmetal1)
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l2n.connect(rmetal1, rvia1)
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l2n.connect(rvia1, rmetal2)
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l2n.connect(rpoly, rpoly_lbl) # attaches labels
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l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
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l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
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# Perform netlist extraction
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l2n.extract_netlist
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assert_equal(l2n.netlist.to_s, <<END)
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Circuit TRANS ($1=$1,$2=$2,$3=$3):
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Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):
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XTRANS $1 ($1=$2,$2=$4,$3=IN)
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XTRANS $2 ($1=$2,$2=$5,$3=IN)
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XTRANS $3 ($1=$5,$2=OUT,$3=$2)
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XTRANS $4 ($1=$4,$2=OUT,$3=$2)
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Circuit RINGO ():
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XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)
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XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD)
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XINV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD)
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XINV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD)
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XINV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD)
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XINV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD)
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XINV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD)
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XINV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD)
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XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)
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XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)
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END
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end
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def test_11_LayoutToNetlistExtractionWithDevices
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ly = RBA::Layout::new
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ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l1.gds"))
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
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rnwell = l2n.make_layer( ly.layer(1, 0) )
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ractive = l2n.make_layer( ly.layer(2, 0) )
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rpoly = l2n.make_polygon_layer( ly.layer(3, 0) )
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rpoly_lbl = l2n.make_text_layer( ly.layer(3, 1) )
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rdiff_cont = l2n.make_polygon_layer( ly.layer(4, 0) )
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rpoly_cont = l2n.make_polygon_layer( ly.layer(5, 0) )
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rmetal1 = l2n.make_polygon_layer( ly.layer(6, 0) )
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rmetal1_lbl = l2n.make_text_layer( ly.layer(6, 1) )
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rvia1 = l2n.make_polygon_layer( ly.layer(7, 0) )
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rmetal2 = l2n.make_polygon_layer( ly.layer(8, 0) )
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rmetal2_lbl = l2n.make_text_layer( ly.layer(8, 1) )
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rpactive = ractive & rnwell
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rpgate = rpactive & rpoly
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rpsd = rpactive - rpgate
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rnactive = ractive - rnwell
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rngate = rnactive & rpoly
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rnsd = rnactive - rngate
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# PMOS transistor device extraction
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pmos_ex = RBA::DeviceExtractorMOS3Transistor::new("PMOS")
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l2n.extract_devices(pmos_ex, { "SD" => rpsd, "G" => rpgate, "P" => rpoly })
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# NMOS transistor device extraction
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nmos_ex = RBA::DeviceExtractorMOS3Transistor::new("NMOS")
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l2n.extract_devices(nmos_ex, { "SD" => rnsd, "G" => rngate, "P" => rpoly })
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# Define connectivity for netlist extraction
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# Intra-layer
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l2n.connect(rpsd)
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l2n.connect(rnsd)
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l2n.connect(rpoly)
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l2n.connect(rdiff_cont)
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l2n.connect(rpoly_cont)
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l2n.connect(rmetal1)
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l2n.connect(rvia1)
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l2n.connect(rmetal2)
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# Inter-layer
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l2n.connect(rpsd, rdiff_cont)
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l2n.connect(rnsd, rdiff_cont)
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l2n.connect(rpoly, rpoly_cont)
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l2n.connect(rpoly_cont, rmetal1)
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l2n.connect(rdiff_cont, rmetal1)
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l2n.connect(rmetal1, rvia1)
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l2n.connect(rvia1, rmetal2)
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l2n.connect(rpoly, rpoly_lbl) # attaches labels
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l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
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l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
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# Perform netlist extraction
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l2n.extract_netlist
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assert_equal(l2n.netlist.to_s, <<END)
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Circuit RINGO ():
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XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)
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XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD)
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XINV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD)
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XINV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD)
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XINV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD)
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XINV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD)
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XINV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD)
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XINV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD)
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XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)
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XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)
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Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):
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DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
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DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
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DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
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DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
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XTRANS $1 ($1=$2,$2=$4,$3=IN)
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XTRANS $2 ($1=$2,$2=$5,$3=IN)
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XTRANS $3 ($1=$5,$2=OUT,$3=$2)
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XTRANS $4 ($1=$4,$2=OUT,$3=$2)
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Circuit TRANS ($1=$1,$2=$2,$3=$3):
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END
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# cleanup now
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l2n._destroy
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end
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end
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load("test_epilogue.rb")
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