klayout/testdata/lvs/ringo_simple_dmos.lvsdb.2

#%lvsdb-klayout

# Layout
layout(
 top(RINGO)
 unit(0.001)

 # Layer section
 # This section lists the mask layers (drawing or derived) and their connections.

 # Mask layers
 layer(l4 '1/0')
 layer(l5 '5/0')
 layer(l10 '8/0')
 layer(l13 '9/0')
 layer(l14 '10/0')
 layer(l15 '11/0')
 layer(l9)
 layer(l3)
 layer(l1)
 layer(l11)
 layer(l8)
 layer(l6)
 layer(l12)

 # Mask layer connectivity
 connect(l4 l4 l11)
 connect(l5 l5 l10)
 connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
 connect(l13 l10 l13 l14)
 connect(l14 l13 l14 l15)
 connect(l15 l14 l15)
 connect(l9 l9)
 connect(l3 l10 l3)
 connect(l1 l10 l1)
 connect(l11 l4 l10 l11)
 connect(l8 l10 l8)
 connect(l6 l10 l6)
 connect(l12 l10 l12)

 # Global nets and connectivity
 global(l9 SUBSTRATE)
 global(l12 SUBSTRATE)

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Device abstracts section
 # Device abstracts list the pin shapes of the devices.
 device(D$PMOS PMOS
  terminal(S
   rect(l3 (125 -750) (450 1500))
  )
  terminal(G
   rect(l5 (-125 -750) (250 1500))
  )
  terminal(D
   rect(l1 (-550 -750) (425 1500))
  )
  terminal(B
   rect(l4 (-125 -750) (250 1500))
  )
 )
 device(D$PMOS$1 PMOS
  terminal(S
   rect(l3 (-575 -750) (450 1500))
  )
  terminal(G
   rect(l5 (-125 -750) (250 1500))
  )
  terminal(D
   rect(l1 (125 -750) (425 1500))
  )
  terminal(B
   rect(l4 (-125 -750) (250 1500))
  )
 )
 device(D$PMOS$2 PMOS
  terminal(S
   rect(l3 (-550 -750) (425 1500))
  )
  terminal(G
   rect(l5 (-125 -750) (250 1500))
  )
  terminal(D
   rect(l1 (125 -750) (425 1500))
  )
  terminal(B
   rect(l4 (-125 -750) (250 1500))
  )
 )
 device(D$NMOS NMOS
  terminal(S
   rect(l8 (125 -475) (450 950))
  )
  terminal(G
   rect(l5 (-125 -475) (250 950))
  )
  terminal(D
   rect(l6 (-550 -475) (425 950))
  )
  terminal(B
   rect(l9 (-125 -475) (250 950))
  )
 )
 device(D$NMOS$1 NMOS
  terminal(S
   rect(l8 (-575 -475) (450 950))
  )
  terminal(G
   rect(l5 (-125 -475) (250 950))
  )
  terminal(D
   rect(l6 (125 -475) (425 950))
  )
  terminal(B
   rect(l9 (-125 -475) (250 950))
  )
 )
 device(D$NMOS$2 NMOS
  terminal(S
   rect(l8 (-550 -475) (425 950))
  )
  terminal(G
   rect(l5 (-125 -475) (250 950))
  )
  terminal(D
   rect(l6 (125 -475) (425 950))
  )
  terminal(B
   rect(l9 (-125 -475) (250 950))
  )
 )

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(ND2X1

  # Circuit boundary
  rect((-100 400) (2600 7600))

  # Nets with their geometries
  net(1 name(VDD)
   rect(l10 (1110 5160) (180 180))
   rect(l10 (-180 920) (180 180))
   rect(l10 (-180 -730) (180 180))
   rect(l13 (-240 -790) (300 1700))
   rect(l13 (-1350 0) (2400 800))
   rect(l13 (-1150 -400) (0 0))
   rect(l3 (-250 -2150) (425 1500))
   rect(l3 (-450 -1500) (425 1500))
  )
  net(2 name(OUT)
   rect(l10 (1810 1770) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l10 (-1580 3760) (180 180))
   rect(l10 (-180 -730) (180 180))
   rect(l10 (-180 -730) (180 180))
   rect(l10 (1220 920) (180 180))
   rect(l10 (-180 -1280) (180 180))
   rect(l10 (-180 370) (180 180))
   polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
   rect(l13 (-110 1390) (300 1400))
   polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
   rect(l13 (-140 -500) (0 0))
   rect(l13 (-1750 1100) (300 1400))
   rect(l13 (1100 -1700) (300 300))
   rect(l13 (-300 0) (300 1400))
   rect(l1 (-1750 -1450) (425 1500))
   rect(l1 (950 -1500) (425 1500))
   rect(l6 (-425 -4890) (425 950))
  )
  net(3 name(VSS)
   rect(l10 (410 1770) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l13 (-240 -1300) (300 1360))
   rect(l13 (-650 -2160) (2400 800))
   rect(l13 (-1150 -400) (0 0))
   rect(l6 (-950 860) (425 950))
  )
  net(4 name($4)
   rect(l8 (1000 1660) (425 950))
   rect(l8 (-450 -950) (425 950))
  )
  net(5 name($5)
   rect(l4 (-100 4500) (2600 3500))
  )
  net(6 name(B)
   rect(l5 (1425 2860) (250 1940))
   rect(l5 (-345 -950) (300 300))
   rect(l5 (-205 650) (250 2000))
   rect(l5 (-250 -2000) (250 2000))
   rect(l5 (-250 -5390) (250 1450))
   rect(l10 (-285 1050) (180 180))
   rect(l13 (-70 -90) (0 0))
   rect(l13 (-170 -150) (300 300))
  )
  net(7 name(A)
   rect(l5 (725 2860) (250 1940))
   rect(l5 (-325 -1850) (300 300))
   rect(l5 (-225 1550) (250 2000))
   rect(l5 (-250 -2000) (250 2000))
   rect(l5 (-250 -5390) (250 1450))
   rect(l10 (-265 150) (180 180))
   rect(l13 (-90 -90) (0 0))
   rect(l13 (-150 -150) (300 300))
  )
  net(8 name(SUBSTRATE))

  # Outgoing pins and their connections to nets
  pin(1 name(VDD))
  pin(2 name(OUT))
  pin(3 name(VSS))
  pin(5)
  pin(6 name(B))
  pin(7 name(A))
  pin(8 name(SUBSTRATE))

  # Devices and their connections
  device(1 D$PMOS
   location(850 5800)
   param(L 0.25)
   param(W 1.5)
   param(AS 0.3375)
   param(AD 0.6375)
   param(PS 1.95)
   param(PD 3.85)
   terminal(S 1)
   terminal(G 7)
   terminal(D 2)
   terminal(B 5)
  )
  device(2 D$PMOS$1
   location(1550 5800)
   param(L 0.25)
   param(W 1.5)
   param(AS 0.3375)
   param(AD 0.6375)
   param(PS 1.95)
   param(PD 3.85)
   terminal(S 1)
   terminal(G 6)
   terminal(D 2)
   terminal(B 5)
  )
  device(3 D$NMOS
   location(850 2135)
   param(L 0.25)
   param(W 0.95)
   param(AS 0.21375)
   param(AD 0.40375)
   param(PS 1.4)
   param(PD 2.75)
   terminal(S 4)
   terminal(G 7)
   terminal(D 3)
   terminal(B 8)
  )
  device(4 D$NMOS$1
   location(1550 2135)
   param(L 0.25)
   param(W 0.95)
   param(AS 0.21375)
   param(AD 0.40375)
   param(PS 1.4)
   param(PD 2.75)
   terminal(S 4)
   terminal(G 6)
   terminal(D 2)
   terminal(B 8)
  )

 )
 circuit(INVX1

  # Circuit boundary
  rect((-100 400) (2000 7600))

  # Nets with their geometries
  net(1 name(VDD)
   rect(l10 (410 6260) (180 180))
   rect(l10 (-180 -730) (180 180))
   rect(l10 (-180 -730) (180 180))
   rect(l13 (-240 -240) (300 1400))
   rect(l13 (-650 300) (1800 800))
   rect(l13 (-1450 -1100) (300 300))
   rect(l13 (300 400) (0 0))
   rect(l3 (-650 -2150) (425 1500))
  )
  net(2 name(OUT)
   rect(l10 (1110 5160) (180 180))
   rect(l10 (-180 920) (180 180))
   rect(l10 (-180 -730) (180 180))
   rect(l10 (-180 -4120) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l13 (-240 -790) (300 4790))
   rect(l13 (-150 -2500) (0 0))
   rect(l1 (-225 1050) (425 1500))
   rect(l6 (-425 -4890) (425 950))
  )
  net(3 name(VSS)
   rect(l10 (410 1770) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l13 (-240 -1300) (300 1360))
   rect(l13 (-650 -2160) (1800 800))
   rect(l13 (-850 -400) (0 0))
   rect(l8 (-650 860) (425 950))
  )
  net(4 name($4)
   rect(l4 (-100 4500) (2000 3500))
  )
  net(5 name(IN)
   rect(l5 (725 2860) (250 1940))
   rect(l5 (-525 -1850) (300 300))
   rect(l5 (-25 1550) (250 2000))
   rect(l5 (-250 -2000) (250 2000))
   rect(l5 (-250 -5390) (250 1450))
   rect(l10 (-465 150) (180 180))
   rect(l13 (-90 -90) (0 0))
   rect(l13 (-150 -150) (300 300))
  )
  net(6 name(SUBSTRATE))

  # Outgoing pins and their connections to nets
  pin(1 name(VDD))
  pin(2 name(OUT))
  pin(3 name(VSS))
  pin(4)
  pin(5 name(IN))
  pin(6 name(SUBSTRATE))

  # Devices and their connections
  device(1 D$PMOS$2
   location(850 5800)
   param(L 0.25)
   param(W 1.5)
   param(AS 0.6375)
   param(AD 0.6375)
   param(PS 3.85)
   param(PD 3.85)
   terminal(S 1)
   terminal(G 5)
   terminal(D 2)
   terminal(B 4)
  )
  device(2 D$NMOS$2
   location(850 2135)
   param(L 0.25)
   param(W 0.95)
   param(AS 0.40375)
   param(AD 0.40375)
   param(PS 2.75)
   param(PD 2.75)
   terminal(S 3)
   terminal(G 5)
   terminal(D 2)
   terminal(B 6)
  )

 )
 circuit(RINGO

  # Circuit boundary
  rect((0 350) (25800 7650))

  # Nets with their geometries
  net(1 name($1)
   rect(l13 (4040 2950) (610 300))
  )
  net(2 name($2)
   rect(l13 (5550 2950) (900 300))
  )
  net(3 name($3)
   rect(l13 (7350 2950) (900 300))
  )
  net(4 name($4)
   rect(l13 (9150 2950) (900 300))
  )
  net(5 name($5)
   rect(l13 (10950 2950) (900 300))
  )
  net(6 name($6)
   rect(l13 (12750 2950) (900 300))
  )
  net(7 name($7)
   rect(l13 (14550 2950) (900 300))
  )
  net(8 name($8)
   rect(l13 (16350 2950) (900 300))
  )
  net(9 name($9)
   rect(l13 (18150 2950) (900 300))
  )
  net(10 name($10)
   rect(l13 (19950 2950) (900 300))
  )
  net(11 name(FB)
   rect(l13 (21750 2950) (900 300))
   rect(l13 (-19530 590) (320 320))
   rect(l13 (17820 -320) (320 320))
   rect(l14 (-18400 -260) (200 200))
   rect(l14 (17940 -200) (200 200))
   rect(l15 (-18040 -300) (17740 400))
   rect(l15 (-17920 -200) (0 0))
   rect(l15 (-220 -200) (400 400))
   rect(l15 (17740 -400) (400 400))
  )
  net(12 name(VDD)
   rect(l4 (500 4500) (1400 3500))
   rect(l4 (-1900 -3500) (600 3500))
   rect(l4 (23300 -3500) (1400 3500))
   rect(l4 (-100 -3500) (600 3500))
   rect(l10 (-24690 -1240) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l10 (-180 -1280) (180 180))
   rect(l10 (23220 370) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l10 (-180 -1280) (180 180))
   rect(l13 (-21740 860) (0 0))
   rect(l13 (-2350 -450) (1200 800))
   rect(l13 (-750 -1450) (300 1400))
   rect(l13 (-100 -350) (0 0))
   rect(l13 (-1250 -400) (600 800))
   rect(l13 (23400 -800) (1200 800))
   rect(l13 (-750 -1450) (300 1400))
   rect(l13 (-100 -350) (0 0))
   rect(l13 (550 -400) (600 800))
   rect(l11 (-24850 -1500) (500 1500))
   rect(l11 (22900 -1500) (500 1500))
  )
  net(13 name(OUT)
   rect(l13 (23440 3840) (320 320))
   rect(l14 (-260 -260) (200 200))
   rect(l15 (-100 -100) (0 0))
   rect(l15 (-200 -200) (400 400))
  )
  net(14 name(ENABLE)
   rect(l13 (2440 2940) (320 320))
   rect(l14 (-260 -260) (200 200))
   rect(l15 (-100 -100) (0 0))
   rect(l15 (-200 -200) (400 400))
  )
  net(15 name(VSS)
   rect(l10 (1110 1610) (180 180))
   rect(l10 (-180 -1280) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l10 (23220 370) (180 180))
   rect(l10 (-180 -1280) (180 180))
   rect(l10 (-180 370) (180 180))
   rect(l13 (-21740 -390) (0 0))
   rect(l13 (-1900 -400) (300 1400))
   rect(l13 (-750 -1450) (1200 800))
   rect(l13 (-550 -400) (0 0))
   rect(l13 (-1250 -400) (600 800))
   rect(l13 (23850 -750) (300 1400))
   rect(l13 (-750 -1450) (1200 800))
   rect(l13 (-550 -400) (0 0))
   rect(l13 (550 -400) (600 800))
   rect(l12 (-24850 -800) (500 1500))
   rect(l12 (22900 -1500) (500 1500))
  )

  # Outgoing pins and their connections to nets
  pin(11 name(FB))
  pin(12 name(VDD))
  pin(13 name(OUT))
  pin(14 name(ENABLE))
  pin(15 name(VSS))

  # Subcircuits and their connections
  circuit(1 ND2X1 location(1800 0)
   pin(0 12)
   pin(1 1)
   pin(2 15)
   pin(3 12)
   pin(4 11)
   pin(5 14)
   pin(6 15)
  )
  circuit(2 INVX1 location(4200 0)
   pin(0 12)
   pin(1 2)
   pin(2 15)
   pin(3 12)
   pin(4 1)
   pin(5 15)
  )
  circuit(3 INVX1 location(6000 0)
   pin(0 12)
   pin(1 3)
   pin(2 15)
   pin(3 12)
   pin(4 2)
   pin(5 15)
  )
  circuit(4 INVX1 location(7800 0)
   pin(0 12)
   pin(1 4)
   pin(2 15)
   pin(3 12)
   pin(4 3)
   pin(5 15)
  )
  circuit(5 INVX1 location(9600 0)
   pin(0 12)
   pin(1 5)
   pin(2 15)
   pin(3 12)
   pin(4 4)
   pin(5 15)
  )
  circuit(6 INVX1 location(11400 0)
   pin(0 12)
   pin(1 6)
   pin(2 15)
   pin(3 12)
   pin(4 5)
   pin(5 15)
  )
  circuit(7 INVX1 location(13200 0)
   pin(0 12)
   pin(1 7)
   pin(2 15)
   pin(3 12)
   pin(4 6)
   pin(5 15)
  )
  circuit(8 INVX1 location(15000 0)
   pin(0 12)
   pin(1 8)
   pin(2 15)
   pin(3 12)
   pin(4 7)
   pin(5 15)
  )
  circuit(9 INVX1 location(16800 0)
   pin(0 12)
   pin(1 9)
   pin(2 15)
   pin(3 12)
   pin(4 8)
   pin(5 15)
  )
  circuit(10 INVX1 location(18600 0)
   pin(0 12)
   pin(1 10)
   pin(2 15)
   pin(3 12)
   pin(4 9)
   pin(5 15)
  )
  circuit(11 INVX1 location(20400 0)
   pin(0 12)
   pin(1 11)
   pin(2 15)
   pin(3 12)
   pin(4 10)
   pin(5 15)
  )
  circuit(12 INVX1 location(22200 0)
   pin(0 12)
   pin(1 13)
   pin(2 15)
   pin(3 12)
   pin(4 11)
   pin(5 15)
  )

 )
)

# Reference netlist
reference(

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(ND2X1

  # Nets
  net(1 name(VDD))
  net(2 name(OUT))
  net(3 name(VSS))
  net(4 name(NWELL))
  net(5 name(B))
  net(6 name(A))
  net(7 name(BULK))
  net(8 name('1'))

  # Outgoing pins and their connections to nets
  pin(1 name(VDD))
  pin(2 name(OUT))
  pin(3 name(VSS))
  pin(4 name(NWELL))
  pin(5 name(B))
  pin(6 name(A))
  pin(7 name(BULK))

  # Devices and their connections
  device(1 PMOS
   name($1)
   param(L 0.25)
   param(W 1.5)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 1)
   terminal(G 6)
   terminal(D 2)
   terminal(B 4)
  )
  device(2 PMOS
   name($2)
   param(L 0.25)
   param(W 1.5)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 1)
   terminal(G 5)
   terminal(D 2)
   terminal(B 4)
  )
  device(3 NMOS
   name($3)
   param(L 0.25)
   param(W 0.95)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 3)
   terminal(G 6)
   terminal(D 8)
   terminal(B 7)
  )
  device(4 NMOS
   name($4)
   param(L 0.25)
   param(W 0.95)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 8)
   terminal(G 5)
   terminal(D 2)
   terminal(B 7)
  )

 )
 circuit(INVX1

  # Nets
  net(1 name(VDD))
  net(2 name(OUT))
  net(3 name(VSS))
  net(4 name(NWELL))
  net(5 name(IN))
  net(6 name(BULK))

  # Outgoing pins and their connections to nets
  pin(1 name(VDD))
  pin(2 name(OUT))
  pin(3 name(VSS))
  pin(4 name(NWELL))
  pin(5 name(IN))
  pin(6 name(BULK))

  # Devices and their connections
  device(1 PMOS
   name($1)
   param(L 0.25)
   param(W 1.5)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 1)
   terminal(G 5)
   terminal(D 2)
   terminal(B 4)
  )
  device(2 NMOS
   name($2)
   param(L 0.25)
   param(W 0.95)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 3)
   terminal(G 5)
   terminal(D 2)
   terminal(B 6)
  )

 )
 circuit(RINGO

  # Nets
  net(1 name(VSS))
  net(2 name(VDD))
  net(3 name(FB))
  net(4 name(ENABLE))
  net(5 name(OUT))
  net(6 name('1'))
  net(7 name('2'))
  net(8 name('3'))
  net(9 name('4'))
  net(10 name('5'))
  net(11 name('6'))
  net(12 name('7'))
  net(13 name('8'))
  net(14 name('9'))
  net(15 name('10'))

  # Outgoing pins and their connections to nets
  pin(1 name(VSS))
  pin(2 name(VDD))
  pin(3 name(FB))
  pin(4 name(ENABLE))
  pin(5 name(OUT))

  # Subcircuits and their connections
  circuit(1 ND2X1 name($1)
   pin(0 2)
   pin(1 6)
   pin(2 1)
   pin(3 2)
   pin(4 3)
   pin(5 4)
   pin(6 1)
  )
  circuit(2 INVX1 name($2)
   pin(0 2)
   pin(1 7)
   pin(2 1)
   pin(3 2)
   pin(4 6)
   pin(5 1)
  )
  circuit(3 INVX1 name($3)
   pin(0 2)
   pin(1 8)
   pin(2 1)
   pin(3 2)
   pin(4 7)
   pin(5 1)
  )
  circuit(4 INVX1 name($4)
   pin(0 2)
   pin(1 9)
   pin(2 1)
   pin(3 2)
   pin(4 8)
   pin(5 1)
  )
  circuit(5 INVX1 name($5)
   pin(0 2)
   pin(1 10)
   pin(2 1)
   pin(3 2)
   pin(4 9)
   pin(5 1)
  )
  circuit(6 INVX1 name($6)
   pin(0 2)
   pin(1 11)
   pin(2 1)
   pin(3 2)
   pin(4 10)
   pin(5 1)
  )
  circuit(7 INVX1 name($7)
   pin(0 2)
   pin(1 12)
   pin(2 1)
   pin(3 2)
   pin(4 11)
   pin(5 1)
  )
  circuit(8 INVX1 name($8)
   pin(0 2)
   pin(1 13)
   pin(2 1)
   pin(3 2)
   pin(4 12)
   pin(5 1)
  )
  circuit(9 INVX1 name($9)
   pin(0 2)
   pin(1 14)
   pin(2 1)
   pin(3 2)
   pin(4 13)
   pin(5 1)
  )
  circuit(10 INVX1 name($10)
   pin(0 2)
   pin(1 15)
   pin(2 1)
   pin(3 2)
   pin(4 14)
   pin(5 1)
  )
  circuit(11 INVX1 name($11)
   pin(0 2)
   pin(1 3)
   pin(2 1)
   pin(3 2)
   pin(4 15)
   pin(5 1)
  )
  circuit(12 INVX1 name($12)
   pin(0 2)
   pin(1 5)
   pin(2 1)
   pin(3 2)
   pin(4 3)
   pin(5 1)
  )

 )
)

# Cross reference
xref(
 log(
  entry(error description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n  A: ND2X1\n  B: ND2X1'))
 )
 circuit(INVX1 INVX1 match
  xref(
   net(4 4 match)
   net(5 5 match)
   net(2 2 match)
   net(6 6 match)
   net(1 1 match)
   net(3 3 match)
   pin(3 3 match)
   pin(4 4 match)
   pin(1 1 match)
   pin(5 5 match)
   pin(0 0 match)
   pin(2 2 match)
   device(2 2 match)
   device(1 1 match)
  )
 )
 circuit(ND2X1 ND2X1 nomatch
  log(
   entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
   entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
   entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
  )
  xref(
   net(5 4 match)
   net(4 3 mismatch)
   net(7 6 match)
   net(6 5 match)
   net(2 2 match)
   net(8 7 mismatch)
   net(1 1 match)
   net(3 8 mismatch)
   pin(() 2 mismatch)
   pin(3 3 match)
   pin(5 5 match)
   pin(4 4 match)
   pin(1 1 match)
   pin(6 6 match)
   pin(0 0 match)
   pin(2 () mismatch)
   device(3 3 match)
   device(4 4 mismatch)
   device(1 1 match)
   device(2 2 match)
  )
 )
 circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n  A: ND2X1\n  B: ND2X1')
  xref(
  )
 )
)