klayout/testdata/lvs/enable_wl2.cir

* Extracted by KLayout

* cell Rre
* pin gnd!
* pin vdd!
.SUBCKT Rre 1 2
* net 1 gnd!
* net 2 vdd!
* device instance $1 r0 *1 8.43,1.51 RR1
R$1 1 2 10 RR1 L=6U W=0.6U
.ENDS Rre
Some enhancements * Device#net_for_terminal with terminal name * Spice writer now dumps all parameters for resistors and caps (also secondary) * Enabled Spice writer delegate in LVS (spice_format(...)) * Device class factories for built-in device extractors 2021-07-05 22:22:13 +02:00			`* Extracted by KLayout`

			`* cell Rre`
			`* pin gnd!`
			`* pin vdd!`
			`.SUBCKT Rre 1 2`
			`* net 1 gnd!`
			`* net 2 vdd!`
			`* device instance $1 r0 *1 8.43,1.51 RR1`
Updated doc, reverted netlist writer to write all parameters - it will only write primary parameters for R, L and C 2021-07-05 22:45:40 +02:00			`R$1 1 2 10 RR1 L=6U W=0.6U`
Some enhancements * Device#net_for_terminal with terminal name * Spice writer now dumps all parameters for resistors and caps (also secondary) * Enabled Spice writer delegate in LVS (spice_format(...)) * Device class factories for built-in device extractors 2021-07-05 22:22:13 +02:00			`.ENDS Rre`