mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-22 05:47:31 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
117 lines
2.5 KiB
Verilog
117 lines
2.5 KiB
Verilog
module top;
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reg pass;
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reg signed [7:0] neg = -2;
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reg signed [7:0] m1 = -1;
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reg signed [7:0] zero = 0;
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reg signed [7:0] one = 1;
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reg signed [7:0] pos = 2;
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reg signed [7:0] pose = 2;
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reg signed [7:0] poso = 3;
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reg signed [7:0] res;
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initial begin
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pass = 1'b1;
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#1;
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/* Positive exponent. */
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res = neg**pose;
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if (res !== 4) begin
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$display("Failed neg**pos even, got %d", res);
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pass = 1'b0;
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end
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res = neg**poso;
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if (res !== -8) begin
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$display("Failed neg**pos odd, got %d", res);
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pass = 1'b0;
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end
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res = m1**pose;
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if (res !== 1) begin
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$display("Failed -1**pos even, got %d", res);
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pass = 1'b0;
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end
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res = m1**poso;
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if (res !== -1) begin
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$display("Failed -1**pos odd, got %d", res);
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pass = 1'b0;
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end
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res = zero**pos;
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if (res !== 0) begin
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$display("Failed 0**pos, got %d", res);
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pass = 1'b0;
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end
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res = one**pos;
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if (res !== 1) begin
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$display("Failed 1**pos, got %d", res);
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pass = 1'b0;
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end
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res = pos**pos;
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if (res !== 4) begin
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$display("Failed 1**pos, got %d", res);
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pass = 1'b0;
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end
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/* Zero exponent. */
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res = neg**zero;
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if (res !== 1) begin
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$display("Failed neg**0, got %d", res);
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pass = 1'b0;
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end
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res = m1**zero;
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if (res !== 1) begin
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$display("Failed -1**0, got %d", res);
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pass = 1'b0;
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end
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res = zero**zero;
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if (res !== 1) begin
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$display("Failed 0**0, got %d", res);
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pass = 1'b0;
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end
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res = one**zero;
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if (res !== 1) begin
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$display("Failed 1**0, got %d", res);
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pass = 1'b0;
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end
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res = pos**zero;
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if (res !== 1) begin
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$display("Failed pos**0, got %d", res);
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pass = 1'b0;
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end
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/* Negative exponent. */
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res = neg**m1;
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if (res !== 0) begin
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$display("Failed neg**neg got %d", res);
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pass = 1'b0;
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end
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res = m1**neg;
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if (res !== 1) begin
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$display("Failed -1**neg (even) got %d", res);
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pass = 1'b0;
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end
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res = m1**m1;
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if (res !== -1) begin
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$display("Failed -1**neg (odd) got %d", res);
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pass = 1'b0;
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end
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res = zero**m1;
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if (res !== 'sbx) begin
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$display("Failed 0**neg got %d", res);
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pass = 1'b0;
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end
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res = one**m1;
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if (res !== 1) begin
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$display("Failed 1**neg got %d", res);
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pass = 1'b0;
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end
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res = pos**m1;
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if (res !== 0) begin
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$display("Failed pos**neg got %d", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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