mirror of
https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
100 lines
2.2 KiB
Verilog
100 lines
2.2 KiB
Verilog
/*
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* Copyright (c) 2001 Eric Brombaugh <[email protected]>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// test_simple.v - testbench for simple.mcl behavioral output
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// 01-22-01 E. Brombaugh
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/*
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* The ``simple'' module was generated by the synopsis module compiler
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* and is typical of the modules it generates. The testbench was hand
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* coded. This file was merged into a single file using the Verilog
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* preprocessor.
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*/
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`timescale 1ns / 10 ps
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module simple( y, a, b, c );
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input [3:0] a;
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input [3:0] b;
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input [7:0] c;
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output [8:0] y;
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wire dpa_zero, dpa_one;
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wire [8:0] y_1_;
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assign dpa_zero= 1024'h0;
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assign dpa_one= 1024'h1;
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/* simple.mcl:4 module simple (y, a, b, c); */
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/* simple.mcl:6 input signed [3:0] a, b; */
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/* simple.mcl:7 input signed [7:0] c; */
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/* simple.mcl:9 y = a*b+c; */
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assign y_1_= ((a[2:0]-(a[3]<<3))*(b[2:0]-(b[3]<<3))+(c[6:0]-(c[7]<<7)));
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/* simple.mcl:5 output signed [8:0] y; */
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assign y = y_1_[8:0];
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/* simple.mcl:4 module simple (y, a, b, c); */
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/* simple.mcl:9 y = a*b+c; */
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/*User Defined Aliases */
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endmodule
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module test_simple;
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reg [15:0] count;
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reg clk;
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reg [3:0] a, b;
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reg [7:0] c;
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wire [8:0] y;
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simple u1(y, a, b, c);
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initial
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begin
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count = 0;
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clk = 0;
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a = 0;
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b = 0;
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c = 0;
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end
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always
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#10 clk = ~clk;
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always @(posedge clk)
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begin
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a = count[3:0];
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b = count[7:4];
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c = count[15:8];
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#10
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$display("%h %h %h %h", a, b, c, y);
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count = count + 1;
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if(count == 0)
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$finish(0);
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end
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endmodule
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