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https://github.com/steveicarus/iverilog.git
synced 2026-08-22 05:47:31 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
41 lines
520 B
Verilog
41 lines
520 B
Verilog
typedef logic data_t;
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module dut(i, o);
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input data_t i;
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output data_t o;
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always @* o = i;
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endmodule
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module test();
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data_t i, o;
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dut dut(i, o);
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reg failed = 0;
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initial begin
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i = 1'b0;
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#0 $display(i,,o);
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if (o !== 1'b0) failed = 1;
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i = 1'b1;
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#0 $display(i,,o);
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if (o !== 1'b1) failed = 1;
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i = 1'bx;
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#0 $display(i,,o);
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if (o !== 1'bx) failed = 1;
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i = 1'bz;
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#0 $display(i,,o);
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if (o !== 1'bz) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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