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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
module top;
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reg passed;
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reg [7:0] val;
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reg signed [7:0] sval;
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real rval;
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initial begin
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passed = 1'b1;
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val = 8'hff;
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sval = 8'hff;
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/* Check a constant unsigned value cast to signed. */
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rval = $itor($signed(8'hff));
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if (rval != -1.0) begin
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$display("Failed unsigned constant cast to signed conversion, ",
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"expected -1.0, got %g.", rval);
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passed = 1'b0;
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end
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/* Check an unsigned variable cast to signed. */
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rval = $itor($signed(val));
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if (rval != -1.0) begin
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$display("Failed unsigned variable cast to signed conversion, ",
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"expected -1.0, got %g.", rval);
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passed = 1'b0;
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end
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/* Check a constant signed value. */
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rval = $itor(8'shff);
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if (rval != -1.0) begin
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$display("Failed signed constant conversion, ",
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"expected -1.0, got %g.", rval);
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passed = 1'b0;
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end
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/* Check a variable signed value. */
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rval = $itor(sval);
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if (rval != -1.0) begin
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$display("Failed signed variable conversion, ",
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"expected -1.0, got %g.", rval);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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