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https://github.com/steveicarus/iverilog.git
synced 2026-08-22 13:57:18 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
30 lines
356 B
Verilog
30 lines
356 B
Verilog
module top;
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wire [2:0] value = 2;
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shim shim(
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.bit0(value[0]),
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.bit1(value[1]),
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.bit2(value[2])
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);
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endmodule
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module shim(
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inout wire bit0,
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inout wire bit1,
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inout wire bit2
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);
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wire [2:0] value = {bit2, bit1, bit0};
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initial begin
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#1 $display(value);
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if (value === 2)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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