73 lines
1.1 KiB
Plaintext
73 lines
1.1 KiB
Plaintext
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// Standard definitions for Verilog-AMS
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`ifdef DISCIPLINES_VAMS
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`else
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`define DISCIPLINES_VAMS 1
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discipline \logic ;
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domain discrete;
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enddiscipline
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discipline ddiscrete;
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domain discrete;
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enddiscipline
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nature Current;
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units = "A";
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access = I;
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idt_nature = Charge;
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`ifdef CURRENT_ABSTOL
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abstol = `CURRENT_ABSTOL
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`else
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abstol = 1e-12;
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`endif
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endnature
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nature Charge;
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units = "coul";
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access = Q;
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ddt_nature = Current;
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`ifdef CHARGE_ABSTOL
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abstol = `CHARGE_ABSTOL;
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`else
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abstol = 1e-14;
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`endif
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endnature
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nature Voltage;
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units = "V";
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access = V;
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idt_nature = Flux;
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`ifdef VOLTAGE_ABSTOL
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abstol = `VOLTAGE_ABSTOL;
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`else
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abstol = 1e-6;
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`endif
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endnature
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nature Flux;
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units = "Wb";
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access = Phi;
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ddt_nature = Voltage;
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`ifdef FLUX_ABSTOL
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abstol = `flux_ABSTOL;
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`else
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abstol = 1e-9;
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`endif
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endnature
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discipline electrical;
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potential Voltage;
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flow Current;
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enddiscipline
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discipline voltage;
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potential Voltage;
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enddiscipline
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discipline current;
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flow Current;
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enddiscipline
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`endif // !`ifdef DISCIPLINES_VAMS
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