59 lines
961 B
Verilog
59 lines
961 B
Verilog
// Check that assignment operators are supported on static class properties.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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static integer x;
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endclass
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integer i;
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C c;
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initial begin
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c = new;
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c.x = 1;
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c.x += 5;
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`check(c.x, 6);
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c.x -= 2;
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`check(c.x, 4);
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c.x *= 25;
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`check(c.x, 100);
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c.x /= 5;
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`check(c.x, 20);
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c.x %= 3;
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`check(c.x, 2);
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c.x = 'haa;
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c.x &= 'h33;
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`check(c.x, 'h22);
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c.x |= 'h11;
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`check(c.x, 'h33);
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c.x ^= 'h22;
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`check(c.x, 'h11);
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c.x <<= 3;
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`check(c.x, 'h88);
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c.x <<<= 1;
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`check(c.x, 'h110);
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c.x >>= 2;
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`check(c.x, 'h44);
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c.x >>>= 1;
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`check(c.x, 'h22);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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