26 lines
691 B
Verilog
26 lines
691 B
Verilog
module test;
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// genvar does not increment.
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for (genvar gv1 = -1; gv1 <= 2; gv1 = -1);
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// genvar duplicates.
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for (genvar gv2 = 0; gv2 >= 0; gv2 = gv2 === 1 ? gv2 - 1 : gv2 + 1);
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// undefined value in initialization
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for (genvar gv3 = 1'bx; gv3 <= 1; gv3 = gv3 + 1);
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// undefined value in increment
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for (genvar gv4 = 0; gv4 <= 1; gv4 = gv4 + 1'bx);
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// undefined value in test condition
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for (genvar gv5 = 0; 1'bx; gv5 = gv5 + 1);
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// genvar used in RHS of initialization
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for (genvar gv6 = gv6 + 1; gv <= 1; gv6 = gv6 + 1);
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// loop forever
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for (genvar gv7 = 0; 1'b1; gv7 = gv7 + 1);
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// Almost forever
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for (genvar gv8 = 0; gv8 >= 0; gv8 = gv8 + 1);
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endmodule
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