18 lines
732 B
Verilog
18 lines
732 B
Verilog
module ArraySliceWithNarrowStart(
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input wire [159:0] a,
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input wire start,
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output wire [95:0] out
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);
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wire [31:0] a_unflattened[0:4];
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assign a_unflattened[0] = a[31:0];
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assign a_unflattened[1] = a[63:32];
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assign a_unflattened[2] = a[95:64];
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assign a_unflattened[3] = a[127:96];
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assign a_unflattened[4] = a[159:128];
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wire [31:0] array_slice_6[0:2];
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assign array_slice_6[0] = a_unflattened[{2'h0, start} > 3'h4 ? 3'h4 : {2'h0, start} + 3'h0];
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assign array_slice_6[1] = a_unflattened[{2'h0, start} > 3'h3 ? 3'h4 : {2'h0, start} + 3'h1];
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assign array_slice_6[2] = a_unflattened[{2'h0, start} > 3'h2 ? 3'h4 : {2'h0, start} + 3'h2];
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assign out = {array_slice_6[2], array_slice_6[1], array_slice_6[0]};
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endmodule
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