441 lines
12 KiB
C++
441 lines
12 KiB
C++
#ifndef __Statement_H
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#define __Statement_H
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/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: Statement.h,v 1.20 1999/09/29 18:36:02 steve Exp $"
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#endif
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# include <string>
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# include "svector.h"
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# include "PDelays.h"
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# include "PExpr.h"
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# include "LineInfo.h"
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class PExpr;
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class Statement;
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class PEventStatement;
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/*
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* The PProcess is the root of a behavioral process. Each process gets
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* one of these, which contains its type (initial or always) and a
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* pointer to the single statement that is the process. A module may
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* have several concurrent processes.
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*/
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class PProcess : public LineInfo {
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public:
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enum Type { PR_INITIAL, PR_ALWAYS };
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PProcess(Type t, Statement*st)
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: type_(t), statement_(st) { }
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virtual ~PProcess();
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Type type() const { return type_; }
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Statement*statement() { return statement_; }
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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Type type_;
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Statement*statement_;
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};
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/*
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* The PProcess is a process, the Statement is the actual action. In
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* fact, the Statement class is abstract and represents all the
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* possible kinds of statements that exist in Verilog.
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*/
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class Statement : public LineInfo {
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public:
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Statement() { }
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virtual ~Statement() =0;
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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};
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/*
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* Assignment statements of the various forms are handled by this
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* type. The rvalue is an expression. The lvalue needs to be figured
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* out by the parser as much as possible.
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*/
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class PAssign_ : public Statement {
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public:
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explicit PAssign_(PExpr*lval, PExpr*ex);
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explicit PAssign_(PExpr*lval, PExpr*de, PExpr*ex);
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explicit PAssign_(PExpr*lval, PEventStatement*de, PExpr*ex);
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virtual ~PAssign_() =0;
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const PExpr* lval() const { return lval_; }
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const PExpr* rval() const { return rval_; }
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protected:
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NetNet*elaborate_lval(Design*, const string&path,
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unsigned&lsb, unsigned&msb,
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NetExpr*&mux) const;
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PDelays delay_;
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PEventStatement*event_;
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private:
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PExpr* lval_;
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PExpr* rval_;
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};
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class PAssign : public PAssign_ {
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public:
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explicit PAssign(PExpr*lval, PExpr*ex);
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explicit PAssign(PExpr*lval, PExpr*de, PExpr*ex);
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explicit PAssign(PExpr*lval, PEventStatement*de, PExpr*ex);
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~PAssign();
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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private:
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NetProc*assign_to_memory_(class NetMemory*, PExpr*,
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Design*des, const string&path) const;
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};
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class PAssignNB : public PAssign_ {
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public:
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explicit PAssignNB(PExpr*lval, PExpr*ex);
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explicit PAssignNB(PExpr*lval, PExpr*de, PExpr*ex);
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~PAssignNB();
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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private:
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NetProc*assign_to_memory_(class NetMemory*, PExpr*,
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Design*des, const string&path) const;
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};
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/*
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* A block statement is an ordered list of statements that make up the
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* block. The block can be sequential or parallel, which only affects
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* how the block is interpreted. The parser collects the list of
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* statements before constructing this object, so it knows a priori
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* what is contained.
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*/
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class PBlock : public Statement {
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public:
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enum BL_TYPE { BL_SEQ, BL_PAR };
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explicit PBlock(const string&n, BL_TYPE t, const svector<Statement*>&st);
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explicit PBlock(BL_TYPE t, const svector<Statement*>&st);
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explicit PBlock(BL_TYPE t);
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~PBlock();
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BL_TYPE bl_type() const { return bl_type_; }
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//unsigned size() const { return list_.count(); }
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//const Statement*stat(unsigned idx) const { return list_[idx]; }
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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private:
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string name_;
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const BL_TYPE bl_type_;
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svector<Statement*>list_;
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};
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class PCallTask : public Statement {
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public:
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explicit PCallTask(const string&n, const svector<PExpr*>&parms);
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string name() const { return name_; }
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unsigned nparms() const { return parms_.count(); }
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PExpr*&parm(unsigned idx)
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{ assert(idx < parms_.count());
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return parms_[idx];
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}
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PExpr* parm(unsigned idx) const
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{ assert(idx < parms_.count());
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return parms_[idx];
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}
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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private:
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NetProc* elaborate_sys(Design*des, const string&path) const;
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NetProc* elaborate_usr(Design*des, const string&path) const;
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const string name_;
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svector<PExpr*> parms_;
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};
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class PCase : public Statement {
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public:
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struct Item {
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svector<PExpr*>expr;
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Statement*stat;
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};
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PCase(NetCase::TYPE, PExpr*ex, svector<Item*>*);
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~PCase();
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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NetCase::TYPE type_;
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PExpr*expr_;
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svector<Item*>*items_;
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private: // not implemented
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PCase(const PCase&);
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PCase& operator= (const PCase&);
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};
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class PCondit : public Statement {
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public:
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PCondit(PExpr*ex, Statement*i, Statement*e)
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: expr_(ex), if_(i), else_(e) { }
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~PCondit();
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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PExpr*expr_;
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Statement*if_;
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Statement*else_;
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private: // not implemented
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PCondit(const PCondit&);
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PCondit& operator= (const PCondit&);
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};
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class PDelayStatement : public Statement {
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public:
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PDelayStatement(PExpr*d, Statement*st)
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: delay_(d), statement_(st) { }
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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private:
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PExpr*delay_;
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Statement*statement_;
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};
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class PEventStatement : public Statement {
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public:
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PEventStatement(const svector<PEEvent*>&ee)
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: expr_(ee), statement_(0) { }
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PEventStatement(PEEvent*ee)
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: expr_(1), statement_(0) { expr_[0] = ee; }
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void set_statement(Statement*st) { statement_ = st; }
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virtual void dump(ostream&out, unsigned ind) const;
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virtual NetProc* elaborate(Design*des, const string&path) const;
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// This method is used to elaborate, but attach a previously
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// elaborated statement to the event.
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NetProc* elaborate_st(Design*des, const string&path, NetProc*st) const;
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private:
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svector<PEEvent*>expr_;
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Statement*statement_;
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};
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class PForever : public Statement {
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public:
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explicit PForever(Statement*s);
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~PForever();
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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Statement*statement_;
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};
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class PForStatement : public Statement {
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public:
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PForStatement(PExpr*n1, PExpr*e1, PExpr*cond,
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PExpr*n2, PExpr*e2, Statement*st)
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: name1_(n1), expr1_(e1), cond_(cond), name2_(n2), expr2_(e2),
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statement_(st)
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{ }
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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PExpr* name1_;
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PExpr* expr1_;
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PExpr*cond_;
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PExpr* name2_;
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PExpr* expr2_;
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Statement*statement_;
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};
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class PNoop : public Statement {
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public:
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PNoop() { }
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};
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class PRepeat : public Statement {
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public:
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explicit PRepeat(PExpr*expr, Statement*s);
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~PRepeat();
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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PExpr*expr_;
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Statement*statement_;
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};
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class PWhile : public Statement {
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public:
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PWhile(PExpr*e1, Statement*st)
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: cond_(e1), statement_(st) { }
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~PWhile();
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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PExpr*cond_;
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Statement*statement_;
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};
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/*
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* $Log: Statement.h,v $
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* Revision 1.20 1999/09/29 18:36:02 steve
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* Full case support
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*
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* Revision 1.19 1999/09/22 02:00:48 steve
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* assignment with blocking event delay.
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*
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* Revision 1.18 1999/09/15 01:55:06 steve
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* Elaborate non-blocking assignment to memories.
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*
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* Revision 1.17 1999/09/04 19:11:46 steve
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* Add support for delayed non-blocking assignments.
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*
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* Revision 1.16 1999/09/02 01:59:27 steve
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* Parse non-blocking assignment delays.
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*
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* Revision 1.15 1999/07/12 00:59:36 steve
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* procedural blocking assignment delays.
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*
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* Revision 1.14 1999/07/03 02:12:51 steve
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* Elaborate user defined tasks.
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*
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* Revision 1.13 1999/06/24 04:24:18 steve
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* Handle expression widths for EEE and NEE operators,
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* add named blocks and scope handling,
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* add registers declared in named blocks.
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*
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* Revision 1.12 1999/06/19 21:06:16 steve
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* Elaborate and supprort to vvm the forever
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* and repeat statements.
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*
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* Revision 1.11 1999/06/15 05:38:39 steve
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* Support case expression lists.
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*
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* Revision 1.10 1999/06/13 23:51:16 steve
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* l-value part select for procedural assignments.
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*
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* Revision 1.9 1999/06/06 20:45:38 steve
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* Add parse and elaboration of non-blocking assignments,
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* Replace list<PCase::Item*> with an svector version,
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* Add integer support.
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*
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* Revision 1.8 1999/05/10 00:16:58 steve
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* Parse and elaborate the concatenate operator
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* in structural contexts, Replace vector<PExpr*>
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* and list<PExpr*> with svector<PExpr*>, evaluate
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* constant expressions with parameters, handle
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* memories as lvalues.
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*
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* Parse task declarations, integer types.
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*
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* Revision 1.7 1999/04/29 02:16:26 steve
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* Parse OR of event expressions.
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*
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* Revision 1.6 1999/02/03 04:20:11 steve
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* Parse and elaborate the Verilog CASE statement.
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*
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* Revision 1.5 1999/01/25 05:45:56 steve
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* Add the LineInfo class to carry the source file
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* location of things. PGate, Statement and PProcess.
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*
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* elaborate handles module parameter mismatches,
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* missing or incorrect lvalues for procedural
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* assignment, and errors are propogated to the
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* top of the elaboration call tree.
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*
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* Attach line numbers to processes, gates and
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* assignment statements.
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*
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* Revision 1.4 1998/11/11 03:13:04 steve
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* Handle while loops.
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*
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* Revision 1.3 1998/11/09 18:55:33 steve
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* Add procedural while loops,
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* Parse procedural for loops,
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* Add procedural wait statements,
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* Add constant nodes,
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* Add XNOR logic gate,
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* Make vvm output look a bit prettier.
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*
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* Revision 1.2 1998/11/07 17:05:05 steve
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* Handle procedural conditional, and some
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* of the conditional expressions.
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*
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* Elaborate signals and identifiers differently,
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* allowing the netlist to hold signal information.
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*
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* Revision 1.1 1998/11/03 23:28:56 steve
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* Introduce verilog to CVS.
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*
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*/
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#endif
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