2871 lines
83 KiB
C++
2871 lines
83 KiB
C++
/*
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* Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.111 1999/10/07 05:25:33 steve Exp $"
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#endif
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/*
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* Elaboration takes as input a complete parse tree and the name of a
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* root module, and generates as output the elaborated design. This
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* elaborated design is presented as a Module, which does not
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* reference any other modules. It is entirely self contained.
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*/
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# include <typeinfo>
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# include <strstream>
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# include "pform.h"
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# include "netlist.h"
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# include "netmisc.h"
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string Design::local_symbol(const string&path)
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{
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strstream res;
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res << "_L" << (lcounter_++) << ends;
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return path + "." + res.str();
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}
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static void do_assign(Design*des, const string&path,
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NetNet*lval, NetNet*rval)
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{
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assert(lval->pin_count() == rval->pin_count());
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const unsigned pin_count = lval->pin_count();
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if (NetTmp* tmp = dynamic_cast<NetTmp*>(rval)) {
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for (unsigned idx = 0 ; idx < pin_count ; idx += 1)
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connect(lval->pin(idx), tmp->pin(idx));
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delete tmp;
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if ((tmp = dynamic_cast<NetTmp*>(lval)))
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delete tmp;
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} else if (NetTmp* tmp = dynamic_cast<NetTmp*>(lval)) {
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for (unsigned idx = 0 ; idx < pin_count ; idx += 1)
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connect(tmp->pin(idx), rval->pin(idx));
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delete tmp;
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} else if (rval->local_flag()) {
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for (unsigned idx = 0 ; idx < pin_count ; idx += 1)
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connect(lval->pin(idx), rval->pin(idx));
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delete rval;
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} else if (lval->local_flag()) {
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for (unsigned idx = 0 ; idx < pin_count ; idx += 1)
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connect(lval->pin(idx), rval->pin(idx));
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delete lval;
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} else for (unsigned idx = 0 ; idx < pin_count ; idx += 1) {
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NetBUFZ*cur = new NetBUFZ(des->local_symbol(path));
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connect(cur->pin(0), lval->pin(idx));
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connect(cur->pin(1), rval->pin(idx));
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des->add_node(cur);
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}
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}
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// Urff, I don't like this global variable. I *will* figure out a
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// way to get rid of it. But, for now the PGModule::elaborate method
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// needs it to find the module definition.
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static const map<string,Module*>* modlist = 0;
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static const map<string,PUdp*>* udplist = 0;
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/*
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* Elaborate a source wire. The "wire" is the declaration of wires,
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* registers, ports and memories. The parser has already merged the
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* multiple properties of a wire (i.e. "input wire") so come the
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* elaboration this creates an object in the design that represent the
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* defined item.
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*/
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void PWire::elaborate(Design*des, const string&path) const
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{
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NetNet::Type wtype = type_;
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if (wtype == NetNet::IMPLICIT)
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wtype = NetNet::WIRE;
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if (wtype == NetNet::IMPLICIT_REG)
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wtype = NetNet::REG;
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unsigned wid = 1;
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long lsb = 0, msb = 0;
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if (msb_.count()) {
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svector<long>mnum (msb_.count());
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svector<long>lnum (msb_.count());
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/* There may be multiple declarations of ranges, because
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the symbol may have its range declared in i.e. input
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and reg declarations. Calculate *all* the numbers
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here. I will resolve the values later. */
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for (unsigned idx = 0 ; idx < msb_.count() ; idx += 1) {
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verinum*mval = msb_[idx]->eval_const(des,path);
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if (mval == 0) {
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cerr << msb_[idx]->get_line() << ": error: "
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"Unable to evaluate constant expression ``" <<
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*msb_[idx] << "''." << endl;
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des->errors += 1;
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return;
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}
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verinum*lval = lsb_[idx]->eval_const(des, path);
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if (mval == 0) {
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cerr << lsb_[idx]->get_line() << ": error: "
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"Unable to evaluate constant expression ``" <<
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*lsb_[idx] << "''." << endl;
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des->errors += 1;
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return;
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}
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mnum[idx] = mval->as_long();
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lnum[idx] = lval->as_long();
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delete mval;
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delete lval;
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}
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/* Make sure all the values for msb and lsb match by
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value. If not, report an error. */
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for (unsigned idx = 1 ; idx < msb_.count() ; idx += 1) {
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if ((mnum[idx] != mnum[0]) || (lnum[idx] != lnum[0])) {
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cerr << get_line() << ": error: Inconsistent width, "
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"[" << mnum[idx] << ":" << lnum[idx] << "]"
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" vs. [" << mnum[0] << ":" << lnum[0] << "]"
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" for signal ``" << name_ << "''" << endl;
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des->errors += 1;
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return;
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}
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}
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lsb = lnum[0];
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msb = mnum[0];
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if (mnum[0] > lnum[0])
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wid = mnum[0] - lnum[0] + 1;
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else
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wid = lnum[0] - mnum[0] + 1;
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}
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if (lidx_ || ridx_) {
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assert(lidx_ && ridx_);
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// If the register has indices, then this is a
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// memory. Create the memory object.
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verinum*lval = lidx_->eval_const(des, path);
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assert(lval);
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verinum*rval = ridx_->eval_const(des, path);
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assert(rval);
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long lnum = lval->as_long();
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long rnum = rval->as_long();
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delete lval;
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delete rval;
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NetMemory*sig = new NetMemory(path+"."+name_, wid, lnum, rnum);
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sig->set_attributes(attributes);
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des->add_memory(sig);
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} else {
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NetNet*sig = new NetNet(path + "." + name_, wtype, msb, lsb);
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sig->set_line(*this);
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sig->port_type(port_type_);
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sig->set_attributes(attributes);
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verinum::V iv = verinum::Vz;
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if (wtype == NetNet::REG)
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iv = verinum::Vx;
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for (unsigned idx = 0 ; idx < wid ; idx += 1)
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sig->set_ival(idx, iv);
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des->add_signal(sig);
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}
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}
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void PGate::elaborate(Design*des, const string&path) const
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{
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cerr << "internal error: what kind of gate? " <<
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typeid(*this).name() << endl;
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}
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/*
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* Elaborate the continuous assign. (This is *not* the procedural
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* assign.) Elaborate the lvalue and rvalue, and do the assignment.
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*/
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void PGAssign::elaborate(Design*des, const string&path) const
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{
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unsigned long rise_time, fall_time, decay_time;
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eval_delays(des, path, rise_time, fall_time, decay_time);
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assert(pin(0));
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assert(pin(1));
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/* Elaborate the l-value. */
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NetNet*lval = pin(0)->elaborate_lnet(des, path);
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if (lval == 0) {
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des->errors += 1;
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return;
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}
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/* Elaborate the r-value. Account for the initial decays,
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which are going to be attached to the last gate before the
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generated NetNet. */
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NetNet*rval = pin(1)->elaborate_net(des, path, rise_time,
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fall_time, decay_time);
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if (rval == 0) {
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cerr << get_line() << ": error: Unable to elaborate r-value: "
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<< *pin(1) << endl;
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des->errors += 1;
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return;
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}
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assert(lval && rval);
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if (lval->pin_count() != rval->pin_count()) {
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cerr << get_line() << ": error: lval width (" <<
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lval->pin_count() << ") != rval width (" <<
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rval->pin_count() << ")." << endl;
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delete lval;
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delete rval;
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des->errors += 1;
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return;
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}
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do_assign(des, path, lval, rval);
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}
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/*
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* Elaborate a Builtin gate. These normally get translated into
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* NetLogic nodes that reflect the particular logic function.
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*/
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void PGBuiltin::elaborate(Design*des, const string&path) const
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{
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unsigned count = 1;
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unsigned low = 0, high = 0;
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string name = get_name();
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if (name == "")
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name = des->local_symbol(path);
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/* If the verilog source has a range specification for the
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gates, then I am expected to make more then one
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gate. Figure out how many are desired. */
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if (msb_) {
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verinum*msb = msb_->eval_const(des, path);
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verinum*lsb = lsb_->eval_const(des, path);
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if (msb == 0) {
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cerr << get_line() << ": error: Unable to evaluate "
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"expression " << *msb_ << endl;
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des->errors += 1;
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return;
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}
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if (lsb == 0) {
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cerr << get_line() << ": error: Unable to evaluate "
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"expression " << *lsb_ << endl;
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des->errors += 1;
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return;
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}
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if (msb->as_long() > lsb->as_long())
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count = msb->as_long() - lsb->as_long() + 1;
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else
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count = lsb->as_long() - msb->as_long() + 1;
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low = lsb->as_long();
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high = msb->as_long();
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}
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/* Allocate all the getlist nodes for the gates. */
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NetLogic**cur = new NetLogic*[count];
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assert(cur);
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/* Calculate the gate delays from the delay expressions
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given in the source. For logic gates, the decay time
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is meaningless because it can never go to high
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impedence. However, the bufif devices can generate
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'bz output, so we will pretend that anything can.
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If only one delay value expression is given (i.e. #5
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nand(foo,...)) then rise, fall and decay times are
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all the same value. If two values are given, rise and
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fall times are use, and the decay time is the minimum
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of the rise and fall times. Finally, if all three
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values are given, they are taken as specified. */
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unsigned long rise_time, fall_time, decay_time;
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eval_delays(des, path, rise_time, fall_time, decay_time);
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/* Now make as many gates as the bit count dictates. Give each
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a unique name, and set the delay times. */
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for (unsigned idx = 0 ; idx < count ; idx += 1) {
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strstream tmp;
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unsigned index;
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if (low < high)
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index = low + idx;
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else
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index = low - idx;
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tmp << name << "<" << index << ">";
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const string inm = tmp.str();
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switch (type()) {
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case AND:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::AND);
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break;
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case BUF:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUF);
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break;
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case BUFIF0:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF0);
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break;
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case BUFIF1:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF1);
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break;
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case NAND:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NAND);
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break;
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case NOR:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOR);
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break;
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case NOT:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOT);
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break;
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case OR:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::OR);
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break;
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case XNOR:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XNOR);
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break;
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case XOR:
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cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XOR);
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break;
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}
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cur[idx]->rise_time(rise_time);
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cur[idx]->fall_time(fall_time);
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cur[idx]->decay_time(decay_time);
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des->add_node(cur[idx]);
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}
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/* The gates have all been allocated, this loop runs through
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the parameters and attaches the ports of the objects. */
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for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
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const PExpr*ex = pin(idx);
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NetNet*sig = ex->elaborate_net(des, path);
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if (sig == 0)
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continue;
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assert(sig);
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if (sig->pin_count() == 1)
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for (unsigned gdx = 0 ; gdx < count ; gdx += 1)
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connect(cur[gdx]->pin(idx), sig->pin(0));
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else if (sig->pin_count() == count)
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for (unsigned gdx = 0 ; gdx < count ; gdx += 1)
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connect(cur[gdx]->pin(idx), sig->pin(gdx));
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else {
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cerr << get_line() << ": error: Gate count of " <<
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count << " does not match net width of " <<
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sig->pin_count() << " at pin " << idx << "."
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<< endl;
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des->errors += 1;
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}
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if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
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delete tmp;
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}
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}
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/*
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* Instantiate a module by recursively elaborating it. Set the path of
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* the recursive elaboration so that signal names get properly
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* set. Connect the ports of the instantiated module to the signals of
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* the parameters. This is done with BUFZ gates so that they look just
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* like continuous assignment connections.
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*/
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void PGModule::elaborate_mod_(Design*des, Module*rmod, const string&path) const
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{
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assert(get_name() != "");
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const string my_name = path + "." + get_name();
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const svector<PExpr*>*pins;
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// Detect binding by name. If I am binding by name, then make
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// up a pins array that reflects the positions of the named
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// ports. If this is simply positional binding in the first
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// place, then get the binding from the base class.
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if (pins_) {
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unsigned nexp = rmod->port_count();
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svector<PExpr*>*exp = new svector<PExpr*>(nexp);
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// Scan the bindings, matching them with port names.
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for (unsigned idx = 0 ; idx < npins_ ; idx += 1) {
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// Given a binding, look at the module port names
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// for the position that matches the binding name.
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unsigned pidx = rmod->find_port(pins_[idx].name);
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// If the port name doesn't exist, the find_port
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// method will return the port count. Detect that
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// as an error.
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if (pidx == nexp) {
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cerr << get_line() << ": error: port ``" <<
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pins_[idx].name << "'' is not a port of "
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<< get_name() << "." << endl;
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des->errors += 1;
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continue;
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}
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// If I already bound something to this port, then
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// the (*exp) array will already have a pointer
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// value where I want to place this expression.
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if ((*exp)[pidx]) {
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cerr << get_line() << ": error: port ``" <<
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pins_[idx].name << "'' already bound." <<
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endl;
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des->errors += 1;
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continue;
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}
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// OK, do the binding by placing the expression in
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// the right place.
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(*exp)[pidx] = pins_[idx].parm;
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}
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pins = exp;
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} else {
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if (pin_count() != rmod->port_count()) {
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cerr << get_line() << ": error: Wrong number "
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"of parameters. Expecting " << rmod->port_count() <<
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", got " << pin_count() << "."
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<< endl;
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des->errors += 1;
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return;
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}
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// No named bindings, just use the positional list I
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// already have.
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assert(pin_count() == rmod->port_count());
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pins = get_pins();
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}
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// Elaborate this instance of the module. The recursive
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// elaboration causes the module to generate a netlist with
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// the ports represented by NetNet objects. I will find them
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// later.
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rmod->elaborate(des, my_name, overrides_);
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// Now connect the ports of the newly elaborated designs to
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// the expressions that are the instantiation parameters. Scan
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// the pins, elaborate the expressions attached to them, and
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// bind them to the port of the elaborated module.
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for (unsigned idx = 0 ; idx < pins->count() ; idx += 1) {
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// Skip unconnected module ports.
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if ((*pins)[idx] == 0)
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continue;
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NetNet*sig = (*pins)[idx]->elaborate_net(des, path);
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if (sig == 0) {
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cerr << "internal error: Expression too complicated "
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"for elaboration." << endl;
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continue;
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}
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|
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assert(sig);
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// Inside the module, the port is one or more signals,
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// that were already elaborated. List all those signals,
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// and I will connect them up later.
|
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svector<PWire*> mport = rmod->get_port(idx);
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svector<NetNet*>prts (mport.count());
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|
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unsigned prts_pin_count = 0;
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for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) {
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PWire*pport = mport[ldx];
|
|
prts[ldx] = des->find_signal(my_name, pport->name());
|
|
assert(prts[ldx]);
|
|
prts_pin_count += prts[ldx]->pin_count();
|
|
}
|
|
|
|
// Check that the parts have matching pin counts. If
|
|
// not, they are different widths.
|
|
if (prts_pin_count != sig->pin_count()) {
|
|
cerr << get_line() << ": error: Port " << idx << " of "
|
|
<< type_ << " expects " << prts_pin_count <<
|
|
" pins, got " << sig->pin_count() << " from "
|
|
<< sig->name() << endl;
|
|
des->errors += 1;
|
|
continue;
|
|
}
|
|
|
|
// Connect the sig expression that is the context of the
|
|
// module instance to the ports of the elaborated
|
|
// module.
|
|
|
|
assert(prts_pin_count == sig->pin_count());
|
|
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1) {
|
|
for (unsigned p = 0 ; p < prts[ldx]->pin_count() ; p += 1) {
|
|
prts_pin_count -= 1;
|
|
connect(sig->pin(prts_pin_count),
|
|
prts[ldx]->pin(prts[ldx]->pin_count()-p-1));
|
|
}
|
|
}
|
|
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
|
|
delete tmp;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* From a UDP definition in the source, make a NetUDP
|
|
* object. Elaborate the pin expressions as netlists, then connect
|
|
* those networks to the pins.
|
|
*/
|
|
void PGModule::elaborate_udp_(Design*des, PUdp*udp, const string&path) const
|
|
{
|
|
const string my_name = path+"."+get_name();
|
|
NetUDP*net = new NetUDP(my_name, udp->ports.count(), udp->sequential);
|
|
net->set_attributes(udp->attributes);
|
|
|
|
/* Run through the pins, making netlists for the pin
|
|
expressions and connecting them to the pin in question. All
|
|
of this is independent of the nature of the UDP. */
|
|
for (unsigned idx = 0 ; idx < net->pin_count() ; idx += 1) {
|
|
if (pin(idx) == 0)
|
|
continue;
|
|
|
|
NetNet*sig = pin(idx)->elaborate_net(des, path);
|
|
if (sig == 0) {
|
|
cerr << "internal error: Expression too complicated "
|
|
"for elaboration:" << *pin(idx) << endl;
|
|
continue;
|
|
}
|
|
|
|
connect(sig->pin(0), net->pin(idx));
|
|
|
|
// Delete excess holding signal.
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
|
|
delete tmp;
|
|
}
|
|
|
|
/* Build up the truth table for the netlist from the input
|
|
strings. */
|
|
for (unsigned idx = 0 ; idx < udp->tinput.count() ; idx += 1) {
|
|
string input = udp->sequential
|
|
? (string("") + udp->tcurrent[idx] + udp->tinput[idx])
|
|
: udp->tinput[idx];
|
|
|
|
net->set_table(input, udp->toutput[idx]);
|
|
}
|
|
|
|
net->cleanup_table();
|
|
|
|
if (udp->sequential) switch (udp->initial) {
|
|
case verinum::V0:
|
|
net->set_initial('0');
|
|
break;
|
|
case verinum::V1:
|
|
net->set_initial('1');
|
|
break;
|
|
case verinum::Vx:
|
|
case verinum::Vz:
|
|
net->set_initial('x');
|
|
break;
|
|
}
|
|
|
|
// All done. Add the object to the design.
|
|
des->add_node(net);
|
|
}
|
|
|
|
void PGModule::elaborate(Design*des, const string&path) const
|
|
{
|
|
// Look for the module type
|
|
map<string,Module*>::const_iterator mod = modlist->find(type_);
|
|
if (mod != modlist->end()) {
|
|
elaborate_mod_(des, (*mod).second, path);
|
|
return;
|
|
}
|
|
|
|
// Try a primitive type
|
|
map<string,PUdp*>::const_iterator udp = udplist->find(type_);
|
|
if (udp != udplist->end()) {
|
|
elaborate_udp_(des, (*udp).second, path);
|
|
return;
|
|
}
|
|
|
|
cerr << get_line() << ": error: Unknown module: " << type_ << endl;
|
|
}
|
|
|
|
/*
|
|
* Elaborating binary operations generally involves elaborating the
|
|
* left and right expressions, then making an output wire and
|
|
* connecting the lot together with the right kind of gate.
|
|
*/
|
|
NetNet* PEBinary::elaborate_net(Design*des, const string&path,
|
|
unsigned long rise,
|
|
unsigned long fall,
|
|
unsigned long decay) const
|
|
{
|
|
NetNet*lsig = left_->elaborate_net(des, path),
|
|
*rsig = right_->elaborate_net(des, path);
|
|
if (lsig == 0) {
|
|
cerr << get_line() << ": error: Cannot elaborate ";
|
|
left_->dump(cerr);
|
|
cerr << endl;
|
|
return 0;
|
|
}
|
|
if (rsig == 0) {
|
|
cerr << get_line() << ": error: Cannot elaborate ";
|
|
right_->dump(cerr);
|
|
cerr << endl;
|
|
return 0;
|
|
}
|
|
|
|
NetNet*osig;
|
|
NetNode*gate;
|
|
NetNode*gate_t;
|
|
|
|
switch (op_) {
|
|
case '^': // XOR
|
|
assert(lsig->pin_count() == rsig->pin_count());
|
|
osig = new NetNet(des->local_symbol(path), NetNet::WIRE,
|
|
lsig->pin_count());
|
|
osig->local_flag(true);
|
|
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
|
|
gate = new NetLogic(des->local_symbol(path), 3,
|
|
NetLogic::XOR);
|
|
connect(gate->pin(1), lsig->pin(idx));
|
|
connect(gate->pin(2), rsig->pin(idx));
|
|
connect(gate->pin(0), osig->pin(idx));
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
des->add_node(gate);
|
|
}
|
|
des->add_signal(osig);
|
|
break;
|
|
|
|
case '&': // AND
|
|
assert(lsig->pin_count() == rsig->pin_count());
|
|
osig = new NetNet(des->local_symbol(path), NetNet::WIRE,
|
|
lsig->pin_count());
|
|
osig->local_flag(true);
|
|
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
|
|
gate = new NetLogic(des->local_symbol(path), 3,
|
|
NetLogic::AND);
|
|
connect(gate->pin(1), lsig->pin(idx));
|
|
connect(gate->pin(2), rsig->pin(idx));
|
|
connect(gate->pin(0), osig->pin(idx));
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
des->add_node(gate);
|
|
}
|
|
des->add_signal(osig);
|
|
break;
|
|
|
|
case '|': // Bitwise OR
|
|
assert(lsig->pin_count() == rsig->pin_count());
|
|
osig = new NetNet(des->local_symbol(path), NetNet::WIRE,
|
|
lsig->pin_count());
|
|
osig->local_flag(true);
|
|
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
|
|
gate = new NetLogic(des->local_symbol(path), 3,
|
|
NetLogic::OR);
|
|
connect(gate->pin(1), lsig->pin(idx));
|
|
connect(gate->pin(2), rsig->pin(idx));
|
|
connect(gate->pin(0), osig->pin(idx));
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
des->add_node(gate);
|
|
}
|
|
des->add_signal(osig);
|
|
break;
|
|
|
|
case 'e': // ==
|
|
assert(lsig->pin_count() == rsig->pin_count());
|
|
osig = new NetNet(des->local_symbol(path), NetNet::WIRE);
|
|
osig->local_flag(true);
|
|
gate = new NetLogic(des->local_symbol(path),
|
|
1+lsig->pin_count(),
|
|
NetLogic::AND);
|
|
connect(gate->pin(0), osig->pin(0));
|
|
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
|
|
gate_t = new NetLogic(des->local_symbol(path), 3,
|
|
NetLogic::XNOR);
|
|
connect(gate_t->pin(1), lsig->pin(idx));
|
|
connect(gate_t->pin(2), rsig->pin(idx));
|
|
connect(gate_t->pin(0), gate->pin(idx+1));
|
|
des->add_node(gate_t);
|
|
}
|
|
des->add_signal(osig);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
des->add_node(gate);
|
|
break;
|
|
|
|
case 'n': // !=
|
|
assert(lsig->pin_count() == rsig->pin_count());
|
|
osig = new NetNet(des->local_symbol(path), NetNet::WIRE);
|
|
osig->local_flag(true);
|
|
gate = new NetLogic(des->local_symbol(path),
|
|
1+lsig->pin_count(),
|
|
NetLogic::OR);
|
|
connect(gate->pin(0), osig->pin(0));
|
|
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
|
|
gate_t = new NetLogic(des->local_symbol(path), 3,
|
|
NetLogic::XOR);
|
|
connect(gate_t->pin(1), lsig->pin(idx));
|
|
connect(gate_t->pin(2), rsig->pin(idx));
|
|
connect(gate_t->pin(0), gate->pin(idx+1));
|
|
des->add_node(gate_t);
|
|
}
|
|
des->add_signal(osig);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
des->add_node(gate);
|
|
break;
|
|
|
|
// Elaborate the structural + as an AddSub
|
|
// object. Connect DataA and DataB to the parameters,
|
|
// and connect the output signal to the Result.
|
|
case '+': {
|
|
assert(lsig->pin_count() == rsig->pin_count());
|
|
string name = des->local_symbol(path);
|
|
unsigned width = lsig->pin_count();
|
|
osig = new NetNet(des->local_symbol(path),
|
|
NetNet::WIRE, width);
|
|
NetAddSub*adder = new NetAddSub(name, width);
|
|
for (unsigned idx = 0 ; idx < width ; idx += 1) {
|
|
connect(lsig->pin(idx), adder->pin_DataA(idx));
|
|
connect(rsig->pin(idx), adder->pin_DataB(idx));
|
|
connect(osig->pin(idx), adder->pin_Result(idx));
|
|
}
|
|
gate = adder;
|
|
des->add_signal(osig);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
des->add_node(gate);
|
|
break;
|
|
}
|
|
|
|
default:
|
|
cerr << "internal eror: Unhandled BINARY '" << op_ << "'" << endl;
|
|
osig = 0;
|
|
}
|
|
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(lsig))
|
|
delete tmp;
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(rsig))
|
|
delete tmp;
|
|
|
|
return osig;
|
|
}
|
|
|
|
/*
|
|
* The concatenation operator, as a net, is a wide signal that is
|
|
* connected to all the pins of the elaborated expression nets.
|
|
*/
|
|
NetNet* PEConcat::elaborate_net(Design*des, const string&path,
|
|
unsigned long rise,
|
|
unsigned long fall,
|
|
unsigned long decay) const
|
|
{
|
|
svector<NetNet*>nets (parms_.count());
|
|
unsigned pins = 0;
|
|
unsigned errors = 0;
|
|
|
|
if (repeat_) {
|
|
cerr << get_line() << ": sorry: I do not know how to"
|
|
" elaborate repeat concatenation nets." << endl;
|
|
return 0;
|
|
}
|
|
|
|
/* Elaborate the operands of the concatenation. */
|
|
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
|
|
nets[idx] = parms_[idx]->elaborate_net(des, path, rise,fall,decay);
|
|
if (nets[idx] == 0)
|
|
errors += 1;
|
|
else
|
|
pins += nets[idx]->pin_count();
|
|
}
|
|
|
|
/* If any of the sub expressions failed to elaborate, then
|
|
delete all those that did and abort myself. */
|
|
if (errors) {
|
|
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
|
|
if (nets[idx]) delete nets[idx];
|
|
}
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
/* Make the temporary signal that connects to all the
|
|
operands, and connect it up. Scan the operands of the
|
|
concat operator from least significant to most significant,
|
|
which is opposite from how they are given in the list. */
|
|
NetNet*osig = new NetNet(des->local_symbol(path),
|
|
NetNet::IMPLICIT, pins);
|
|
pins = 0;
|
|
for (unsigned idx = nets.count() ; idx > 0 ; idx -= 1) {
|
|
NetNet*cur = nets[idx-1];
|
|
for (unsigned pin = 0 ; pin < cur->pin_count() ; pin += 1) {
|
|
connect(osig->pin(pins), cur->pin(pin));
|
|
pins += 1;
|
|
}
|
|
}
|
|
|
|
osig->local_flag(true);
|
|
des->add_signal(osig);
|
|
return osig;
|
|
}
|
|
|
|
/*
|
|
* The concatenation is also OK an an l-value. This method elaborates
|
|
* it as a structural l-value.
|
|
*/
|
|
NetNet* PEConcat::elaborate_lnet(Design*des, const string&path) const
|
|
{
|
|
svector<NetNet*>nets (parms_.count());
|
|
unsigned pins = 0;
|
|
unsigned errors = 0;
|
|
|
|
if (repeat_) {
|
|
cerr << get_line() << ": sorry: I do not know how to"
|
|
" elaborate repeat concatenation nets." << endl;
|
|
return 0;
|
|
}
|
|
|
|
/* Elaborate the operands of the concatenation. */
|
|
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
|
|
nets[idx] = parms_[idx]->elaborate_lnet(des, path);
|
|
if (nets[idx] == 0)
|
|
errors += 1;
|
|
else
|
|
pins += nets[idx]->pin_count();
|
|
}
|
|
|
|
/* If any of the sub expressions failed to elaborate, then
|
|
delete all those that did and abort myself. */
|
|
if (errors) {
|
|
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
|
|
if (nets[idx]) delete nets[idx];
|
|
}
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
/* Make the temporary signal that connects to all the
|
|
operands, and connect it up. Scan the operands of the
|
|
concat operator from least significant to most significant,
|
|
which is opposite from how they are given in the list. */
|
|
NetNet*osig = new NetNet(des->local_symbol(path),
|
|
NetNet::IMPLICIT, pins);
|
|
pins = 0;
|
|
for (unsigned idx = nets.count() ; idx > 0 ; idx -= 1) {
|
|
NetNet*cur = nets[idx-1];
|
|
for (unsigned pin = 0 ; pin < cur->pin_count() ; pin += 1) {
|
|
connect(osig->pin(pins), cur->pin(pin));
|
|
pins += 1;
|
|
}
|
|
}
|
|
|
|
osig->local_flag(true);
|
|
des->add_signal(osig);
|
|
return osig;
|
|
}
|
|
|
|
NetNet* PEIdent::elaborate_net(Design*des, const string&path,
|
|
unsigned long rise,
|
|
unsigned long fall,
|
|
unsigned long decay) const
|
|
{
|
|
NetNet*sig = des->find_signal(path, text_);
|
|
if (sig == 0) {
|
|
if (des->find_memory(path+"."+text_)) {
|
|
cerr << get_line() << ": sorry: memories not supported"
|
|
" in this context." << endl;
|
|
return 0;
|
|
}
|
|
sig = new NetNet(path+"."+text_, NetNet::IMPLICIT, 1);
|
|
des->add_signal(sig);
|
|
cerr << get_line() << ": warning: Implicitly defining "
|
|
"wire " << path << "." << text_ << "." << endl;
|
|
}
|
|
|
|
assert(sig);
|
|
|
|
if (msb_ && lsb_) {
|
|
verinum*mval = msb_->eval_const(des, path);
|
|
assert(mval);
|
|
verinum*lval = lsb_->eval_const(des, path);
|
|
assert(lval);
|
|
unsigned midx = sig->sb_to_idx(mval->as_long());
|
|
unsigned lidx = sig->sb_to_idx(lval->as_long());
|
|
|
|
if (midx >= lidx) {
|
|
NetTmp*tmp = new NetTmp(midx-lidx+1);
|
|
if (tmp->pin_count() > sig->pin_count()) {
|
|
cerr << get_line() << ": bit select out of "
|
|
<< "range for " << sig->name() << endl;
|
|
return sig;
|
|
}
|
|
|
|
for (unsigned idx = lidx ; idx <= midx ; idx += 1)
|
|
connect(tmp->pin(idx-lidx), sig->pin(idx));
|
|
|
|
sig = tmp;
|
|
|
|
} else {
|
|
NetTmp*tmp = new NetTmp(lidx-midx+1);
|
|
assert(tmp->pin_count() <= sig->pin_count());
|
|
for (unsigned idx = lidx ; idx >= midx ; idx -= 1)
|
|
connect(tmp->pin(idx-midx), sig->pin(idx));
|
|
|
|
sig = tmp;
|
|
}
|
|
|
|
} else if (msb_) {
|
|
verinum*mval = msb_->eval_const(des, path);
|
|
if (mval == 0) {
|
|
cerr << get_line() << ": index of " << text_ <<
|
|
" needs to be constant in this context." <<
|
|
endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
assert(mval);
|
|
unsigned idx = sig->sb_to_idx(mval->as_long());
|
|
if (idx >= sig->pin_count()) {
|
|
cerr << get_line() << "; index " << sig->name() <<
|
|
"[" << mval->as_long() << "] out of range." << endl;
|
|
des->errors += 1;
|
|
idx = 0;
|
|
}
|
|
NetTmp*tmp = new NetTmp(1);
|
|
connect(tmp->pin(0), sig->pin(idx));
|
|
sig = tmp;
|
|
}
|
|
|
|
return sig;
|
|
}
|
|
|
|
/*
|
|
* Identifiers in continuous assignment l-values are limited to wires
|
|
* and that ilk. Detect registers and memories here and report errors.
|
|
*/
|
|
NetNet* PEIdent::elaborate_lnet(Design*des, const string&path) const
|
|
{
|
|
NetNet*sig = des->find_signal(path, text_);
|
|
if (sig == 0) {
|
|
/* Don't allow memories here. Is it a memory? */
|
|
if (des->find_memory(path+"."+text_)) {
|
|
cerr << get_line() << ": error: memories (" << text_
|
|
<< ") cannot be l-values in continuous "
|
|
<< "assignments." << endl;
|
|
return 0;
|
|
}
|
|
|
|
/* Fine, create an implicit wire as an l-value. */
|
|
sig = new NetNet(path+"."+text_, NetNet::IMPLICIT, 1);
|
|
des->add_signal(sig);
|
|
cerr << get_line() << ": warning: Implicitly defining "
|
|
"wire " << path << "." << text_ << "." << endl;
|
|
}
|
|
|
|
assert(sig);
|
|
|
|
/* Don't allow registers as assign l-values. */
|
|
if (sig->type() == NetNet::REG) {
|
|
cerr << get_line() << ": error: registers (" << sig->name()
|
|
<< ") cannot be l-values in continuous"
|
|
<< " assignments." << endl;
|
|
return 0;
|
|
}
|
|
|
|
if (msb_ && lsb_) {
|
|
/* Detect a part select. Evaluate the bits and elaborate
|
|
the l-value by creating a sub-net that links to just
|
|
the right pins. */
|
|
verinum*mval = msb_->eval_const(des, path);
|
|
assert(mval);
|
|
verinum*lval = lsb_->eval_const(des, path);
|
|
assert(lval);
|
|
unsigned midx = sig->sb_to_idx(mval->as_long());
|
|
unsigned lidx = sig->sb_to_idx(lval->as_long());
|
|
|
|
if (midx >= lidx) {
|
|
NetTmp*tmp = new NetTmp(midx-lidx+1);
|
|
if (tmp->pin_count() > sig->pin_count()) {
|
|
cerr << get_line() << ": bit select out of "
|
|
<< "range for " << sig->name() << endl;
|
|
return sig;
|
|
}
|
|
|
|
for (unsigned idx = lidx ; idx <= midx ; idx += 1)
|
|
connect(tmp->pin(idx-lidx), sig->pin(idx));
|
|
|
|
sig = tmp;
|
|
|
|
} else {
|
|
NetTmp*tmp = new NetTmp(lidx-midx+1);
|
|
assert(tmp->pin_count() <= sig->pin_count());
|
|
for (unsigned idx = lidx ; idx >= midx ; idx -= 1)
|
|
connect(tmp->pin(idx-midx), sig->pin(idx));
|
|
|
|
sig = tmp;
|
|
}
|
|
|
|
} else if (msb_) {
|
|
verinum*mval = msb_->eval_const(des, path);
|
|
if (mval == 0) {
|
|
cerr << get_line() << ": index of " << text_ <<
|
|
" needs to be constant in this context." <<
|
|
endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
assert(mval);
|
|
unsigned idx = sig->sb_to_idx(mval->as_long());
|
|
if (idx >= sig->pin_count()) {
|
|
cerr << get_line() << "; index " << sig->name() <<
|
|
"[" << mval->as_long() << "] out of range." << endl;
|
|
des->errors += 1;
|
|
idx = 0;
|
|
}
|
|
NetTmp*tmp = new NetTmp(1);
|
|
connect(tmp->pin(0), sig->pin(idx));
|
|
sig = tmp;
|
|
}
|
|
|
|
return sig;
|
|
}
|
|
|
|
/*
|
|
*/
|
|
NetNet* PENumber::elaborate_net(Design*des, const string&path,
|
|
unsigned long rise,
|
|
unsigned long fall,
|
|
unsigned long decay) const
|
|
{
|
|
unsigned width = value_->len();
|
|
NetNet*net = new NetNet(des->local_symbol(path),
|
|
NetNet::IMPLICIT, width);
|
|
net->local_flag(true);
|
|
for (unsigned idx = 0 ; idx < width ; idx += 1) {
|
|
NetConst*tmp = new NetConst(des->local_symbol(path),
|
|
value_->get(idx));
|
|
des->add_node(tmp);
|
|
connect(net->pin(idx), tmp->pin(0));
|
|
}
|
|
|
|
des->add_signal(net);
|
|
return net;
|
|
}
|
|
|
|
NetNet* PETernary::elaborate_net(Design*des, const string&path,
|
|
unsigned long rise,
|
|
unsigned long fall,
|
|
unsigned long decay) const
|
|
{
|
|
NetNet* expr_sig = expr_->elaborate_net(des, path);
|
|
NetNet* tru_sig = tru_->elaborate_net(des, path);
|
|
NetNet* fal_sig = fal_->elaborate_net(des, path);
|
|
if (expr_sig == 0 || tru_sig == 0 || fal_sig == 0) {
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
NetNet* sig;
|
|
NetLogic*exprinv;
|
|
NetLogic*and_tru;
|
|
NetLogic*and_fal;
|
|
NetLogic*gate;
|
|
|
|
assert(tru_sig->pin_count() == fal_sig->pin_count());
|
|
assert(expr_sig->pin_count() == 1);
|
|
|
|
sig = new NetNet(des->local_symbol(path), NetNet::WIRE,
|
|
tru_sig->pin_count());
|
|
sig->local_flag(true);
|
|
|
|
for (unsigned idx = 0 ; idx < tru_sig->pin_count() ; idx += 1) {
|
|
exprinv = new NetLogic(des->local_symbol(path), 2, NetLogic::NOT);
|
|
and_tru = new NetLogic(des->local_symbol(path), 3, NetLogic::AND);
|
|
and_fal = new NetLogic(des->local_symbol(path), 3, NetLogic::AND);
|
|
gate = new NetLogic(des->local_symbol(path), 3, NetLogic::OR);
|
|
|
|
connect(exprinv->pin(1), expr_sig->pin(0));
|
|
connect(and_tru->pin(1), expr_sig->pin(0));
|
|
connect(and_fal->pin(1), exprinv->pin(0));
|
|
connect(and_tru->pin(2), tru_sig->pin(idx));
|
|
connect(and_fal->pin(2), fal_sig->pin(idx));
|
|
connect(gate->pin(1), and_tru->pin(0));
|
|
connect(gate->pin(2), and_fal->pin(0));
|
|
connect(gate->pin(0), sig->pin(idx));
|
|
|
|
des->add_node(exprinv);
|
|
des->add_node(and_tru);
|
|
des->add_node(and_fal);
|
|
des->add_node(gate);
|
|
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
}
|
|
|
|
des->add_signal(sig);
|
|
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(expr_sig))
|
|
delete tmp;
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(tru_sig))
|
|
delete tmp;
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(fal_sig))
|
|
delete tmp;
|
|
|
|
return sig;
|
|
}
|
|
|
|
NetNet* PEUnary::elaborate_net(Design*des, const string&path,
|
|
unsigned long rise,
|
|
unsigned long fall,
|
|
unsigned long decay) const
|
|
{
|
|
NetNet* sub_sig = expr_->elaborate_net(des, path);
|
|
if (sub_sig == 0) {
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
assert(sub_sig);
|
|
|
|
NetNet* sig;
|
|
NetLogic*gate;
|
|
switch (op_) {
|
|
case '~': // Bitwise NOT
|
|
sig = new NetNet(des->local_symbol(path), NetNet::WIRE,
|
|
sub_sig->pin_count());
|
|
sig->local_flag(true);
|
|
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) {
|
|
gate = new NetLogic(des->local_symbol(path), 2,
|
|
NetLogic::NOT);
|
|
connect(gate->pin(1), sub_sig->pin(idx));
|
|
connect(gate->pin(0), sig->pin(idx));
|
|
des->add_node(gate);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
}
|
|
des->add_signal(sig);
|
|
break;
|
|
|
|
case 'N': // Reduction NOR
|
|
case '!': // Reduction NOT
|
|
sig = new NetNet(des->local_symbol(path), NetNet::WIRE);
|
|
sig->local_flag(true);
|
|
gate = new NetLogic(des->local_symbol(path),
|
|
1+sub_sig->pin_count(),
|
|
NetLogic::NOR);
|
|
connect(gate->pin(0), sig->pin(0));
|
|
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
|
|
connect(gate->pin(idx+1), sub_sig->pin(idx));
|
|
|
|
des->add_signal(sig);
|
|
des->add_node(gate);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
break;
|
|
|
|
case '&': // Reduction AND
|
|
sig = new NetNet(des->local_symbol(path), NetNet::WIRE);
|
|
sig->local_flag(true);
|
|
gate = new NetLogic(des->local_symbol(path),
|
|
1+sub_sig->pin_count(),
|
|
NetLogic::AND);
|
|
connect(gate->pin(0), sig->pin(0));
|
|
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
|
|
connect(gate->pin(idx+1), sub_sig->pin(idx));
|
|
|
|
des->add_signal(sig);
|
|
des->add_node(gate);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
break;
|
|
|
|
case '|': // Reduction OR
|
|
sig = new NetNet(des->local_symbol(path), NetNet::WIRE);
|
|
sig->local_flag(true);
|
|
gate = new NetLogic(des->local_symbol(path),
|
|
1+sub_sig->pin_count(),
|
|
NetLogic::OR);
|
|
connect(gate->pin(0), sig->pin(0));
|
|
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
|
|
connect(gate->pin(idx+1), sub_sig->pin(idx));
|
|
|
|
des->add_signal(sig);
|
|
des->add_node(gate);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
break;
|
|
|
|
case '^': // Reduction XOR
|
|
sig = new NetNet(des->local_symbol(path), NetNet::WIRE);
|
|
sig->local_flag(true);
|
|
gate = new NetLogic(des->local_symbol(path),
|
|
1+sub_sig->pin_count(),
|
|
NetLogic::XOR);
|
|
connect(gate->pin(0), sig->pin(0));
|
|
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
|
|
connect(gate->pin(idx+1), sub_sig->pin(idx));
|
|
|
|
des->add_signal(sig);
|
|
des->add_node(gate);
|
|
gate->rise_time(rise);
|
|
gate->fall_time(fall);
|
|
gate->decay_time(decay);
|
|
break;
|
|
|
|
default:
|
|
cerr << "internal error: Unhandled UNARY '" << op_ << "'" << endl;
|
|
sig = 0;
|
|
}
|
|
|
|
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sub_sig))
|
|
delete tmp;
|
|
|
|
return sig;
|
|
}
|
|
|
|
NetExpr* PEConcat::elaborate_expr(Design*des, const string&path) const
|
|
{
|
|
unsigned repeat = 1;
|
|
|
|
/* If there is a repeat expression, then evaluate the constant
|
|
value and set the repeat count. */
|
|
if (repeat_) {
|
|
verinum*vrep = repeat_->eval_const(des, path);
|
|
if (vrep == 0) {
|
|
cerr << get_line() << ": error: "
|
|
"concatenation repeat expression cannot be evaluated."
|
|
<< endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
repeat = vrep->as_ulong();
|
|
delete vrep;
|
|
}
|
|
|
|
/* Make the empty concat expression. */
|
|
NetEConcat*tmp = new NetEConcat(parms_.count(), repeat);
|
|
tmp->set_line(*this);
|
|
|
|
/* Elaborate all the parameters and attach them to the concat node. */
|
|
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
|
|
assert(parms_[idx]);
|
|
NetExpr*ex = parms_[idx]->elaborate_expr(des, path);
|
|
if (ex == 0) continue;
|
|
tmp->set(idx, parms_[idx]->elaborate_expr(des, path));
|
|
}
|
|
|
|
return tmp;
|
|
}
|
|
|
|
NetExpr* PENumber::elaborate_expr(Design*des, const string&path) const
|
|
{
|
|
assert(value_);
|
|
NetEConst*tmp = new NetEConst(*value_);
|
|
tmp->set_line(*this);
|
|
return tmp;
|
|
}
|
|
|
|
NetExpr* PEString::elaborate_expr(Design*des, const string&path) const
|
|
{
|
|
NetEConst*tmp = new NetEConst(value());
|
|
tmp->set_line(*this);
|
|
return tmp;
|
|
}
|
|
|
|
NetExpr* PExpr::elaborate_expr(Design*des, const string&path) const
|
|
{
|
|
cerr << get_line() << ": I do not know how to elaborate expression: "
|
|
<< *this << endl;
|
|
return 0;
|
|
}
|
|
|
|
NetExpr* PEUnary::elaborate_expr(Design*des, const string&path) const
|
|
{
|
|
NetEUnary*tmp = new NetEUnary(op_, expr_->elaborate_expr(des, path));
|
|
tmp->set_line(*this);
|
|
return tmp;
|
|
}
|
|
|
|
NetProc* Statement::elaborate(Design*des, const string&path) const
|
|
{
|
|
cerr << "internal error: elaborate: What kind of statement? " <<
|
|
typeid(*this).name() << endl;
|
|
NetProc*cur = new NetProc;
|
|
return cur;
|
|
}
|
|
|
|
NetProc* PAssign::assign_to_memory_(NetMemory*mem, PExpr*ix,
|
|
Design*des, const string&path) const
|
|
{
|
|
NetExpr*rv = rval()->elaborate_expr(des, path);
|
|
if (rv == 0)
|
|
return 0;
|
|
|
|
assert(rv);
|
|
|
|
rv->set_width(mem->width());
|
|
NetExpr*idx = ix->elaborate_expr(des, path);
|
|
assert(idx);
|
|
|
|
NetAssignMem*am = new NetAssignMem(mem, idx, rv);
|
|
am->set_line(*this);
|
|
return am;
|
|
}
|
|
|
|
/*
|
|
* Elaborate an l-value as a NetNet (it may already exist) and make up
|
|
* the part select stuff for where the assignment is going to be made.
|
|
*/
|
|
NetNet* PAssign_::elaborate_lval(Design*des, const string&path,
|
|
unsigned&msb, unsigned&lsb,
|
|
NetExpr*&mux) const
|
|
{
|
|
/* Get the l-value, and assume that it is an identifier. */
|
|
const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
|
|
|
|
/* If the l-value is not a register, then make a structural
|
|
elaboration. Make a synthetic register that connects to the
|
|
generated circuit and return that as the l-value. */
|
|
if (id == 0) {
|
|
NetNet*ll = lval_->elaborate_net(des, path);
|
|
if (ll == 0) {
|
|
cerr << get_line() << ": Assignment l-value too complex."
|
|
<< endl;
|
|
return 0;
|
|
}
|
|
|
|
lsb = 0;
|
|
msb = ll->pin_count()-1;
|
|
mux = 0;
|
|
return ll;
|
|
}
|
|
|
|
assert(id);
|
|
|
|
/* Get the signal referenced by the identifier, and make sure
|
|
it is a register. (Wires are not allows in this context. */
|
|
NetNet*reg = des->find_signal(path, id->name());
|
|
|
|
if (reg == 0) {
|
|
cerr << get_line() << ": error: Could not match signal ``" <<
|
|
id->name() << "'' in ``" << path << "''" << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
assert(reg);
|
|
|
|
if ((reg->type() != NetNet::REG) && (reg->type() != NetNet::INTEGER)) {
|
|
cerr << get_line() << ": error: " << *lval() <<
|
|
" is not a register." << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
if (id->msb_ && id->lsb_) {
|
|
/* This handles part selects. In this case, there are
|
|
two bit select expressions, and both must be
|
|
constant. Evaluate them and pass the results back to
|
|
the caller. */
|
|
verinum*vl = id->lsb_->eval_const(des, path);
|
|
if (vl == 0) {
|
|
cerr << id->lsb_->get_line() << ": error: "
|
|
"Expression must be constant in this context: "
|
|
<< *id->lsb_;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
verinum*vm = id->msb_->eval_const(des, path);
|
|
if (vl == 0) {
|
|
cerr << id->msb_->get_line() << ": error: "
|
|
"Expression must be constant in this context: "
|
|
<< *id->msb_;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
msb = vm->as_ulong();
|
|
lsb = vl->as_ulong();
|
|
mux = 0;
|
|
|
|
} else if (id->msb_) {
|
|
|
|
/* If there is only a single select expression, it is a
|
|
bit select. Evaluate the constant value and treat it
|
|
as a part select with a bit width of 1. If the
|
|
expression it not constant, then return the
|
|
expression as a mux. */
|
|
assert(id->lsb_ == 0);
|
|
verinum*v = id->msb_->eval_const(des, path);
|
|
if (v == 0) {
|
|
NetExpr*m = id->msb_->elaborate_expr(des, path);
|
|
assert(m);
|
|
msb = 0;
|
|
lsb = 0;
|
|
mux = m;
|
|
|
|
} else {
|
|
|
|
msb = v->as_ulong();
|
|
lsb = v->as_ulong();
|
|
mux = 0;
|
|
}
|
|
|
|
} else {
|
|
|
|
/* No select expressions, so presume a part select the
|
|
width of the register. */
|
|
|
|
assert(id->msb_ == 0);
|
|
assert(id->lsb_ == 0);
|
|
msb = reg->msb();
|
|
lsb = reg->lsb();
|
|
mux = 0;
|
|
}
|
|
|
|
return reg;
|
|
}
|
|
|
|
NetProc* PAssign::elaborate(Design*des, const string&path) const
|
|
{
|
|
/* Catch the case where the lvalue is a reference to a memory
|
|
item. These are handled differently. */
|
|
do {
|
|
const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
|
|
if (id == 0) break;
|
|
|
|
if (NetMemory*mem = des->find_memory(path+"."+id->name()))
|
|
return assign_to_memory_(mem, id->msb_, des, path);
|
|
|
|
} while(0);
|
|
|
|
|
|
/* elaborate the lval. This detects any part selects and mux
|
|
expressions that might exist. */
|
|
unsigned lsb, msb;
|
|
NetExpr*mux;
|
|
NetNet*reg = elaborate_lval(des, path, msb, lsb, mux);
|
|
if (reg == 0) return 0;
|
|
|
|
/* If there is a delay expression, elaborate it. */
|
|
unsigned long rise_time, fall_time, decay_time;
|
|
delay_.eval_delays(des, path, rise_time, fall_time, decay_time);
|
|
|
|
|
|
/* Elaborate the r-value expression. */
|
|
assert(rval());
|
|
NetExpr*rv = rval()->elaborate_expr(des, path);
|
|
if (rv == 0)
|
|
return 0;
|
|
|
|
assert(rv);
|
|
|
|
/* Try to evaluate the expression, at least as far as possible. */
|
|
if (NetExpr*tmp = rv->eval_tree()) {
|
|
delete rv;
|
|
rv = tmp;
|
|
}
|
|
|
|
NetAssign*cur;
|
|
|
|
/* Rewrite delayed assignments as assignments that are
|
|
delayed. For example, a = #<d> b; becomes:
|
|
|
|
begin
|
|
tmp = b;
|
|
#<d> a = tmp;
|
|
end
|
|
|
|
If the delay is an event delay, then the transform is
|
|
similar, with the event delay replacing the time delay. It
|
|
is an event delay if the event_ member has a value.
|
|
|
|
This rewriting of the expression allows me to not bother to
|
|
actually and literally represent the delayed assign in the
|
|
netlist. The compound statement is exactly equivalent. */
|
|
|
|
if (rise_time || event_) {
|
|
string n = des->local_symbol(path);
|
|
unsigned wid = reg->pin_count();
|
|
|
|
rv->set_width(reg->pin_count());
|
|
rv = pad_to_width(rv, reg->pin_count());
|
|
|
|
if (! rv->set_width(reg->pin_count())) {
|
|
cerr << get_line() << ": error: Unable to match "
|
|
"expression width of " << rv->expr_width() <<
|
|
" to l-value width of " << wid << "." << endl;
|
|
//XXXX delete rv;
|
|
return 0;
|
|
}
|
|
|
|
NetNet*tmp = new NetNet(n, NetNet::REG, wid);
|
|
tmp->set_line(*this);
|
|
des->add_signal(tmp);
|
|
|
|
/* Generate an assignment of the l-value to the temporary... */
|
|
n = des->local_symbol(path);
|
|
NetAssign*a1 = new NetAssign(n, des, wid, rv);
|
|
a1->set_line(*this);
|
|
des->add_node(a1);
|
|
|
|
for (unsigned idx = 0 ; idx < wid ; idx += 1)
|
|
connect(a1->pin(idx), tmp->pin(idx));
|
|
|
|
/* Generate an assignment of the temporary to the r-value... */
|
|
n = des->local_symbol(path);
|
|
NetESignal*sig = new NetESignal(tmp);
|
|
des->add_node(sig);
|
|
NetAssign*a2 = new NetAssign(n, des, wid, sig);
|
|
a2->set_line(*this);
|
|
des->add_node(a2);
|
|
|
|
for (unsigned idx = 0 ; idx < wid ; idx += 1)
|
|
connect(a2->pin(idx), reg->pin(idx));
|
|
|
|
/* Generate the delay statement with the final
|
|
assignment attached to it. If this is an event delay,
|
|
elaborate the PEventStatement. Otherwise, create the
|
|
right NetPDelay object. */
|
|
NetProc*st;
|
|
if (event_) {
|
|
st = event_->elaborate_st(des, path, a2);
|
|
if (st == 0) {
|
|
cerr << event_->get_line() << ": error: "
|
|
"unable to elaborate event expression."
|
|
<< endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
assert(st);
|
|
|
|
} else {
|
|
NetPDelay*de = new NetPDelay(rise_time, a2);
|
|
st = de;
|
|
}
|
|
|
|
/* And build up the complex statement. */
|
|
NetBlock*bl = new NetBlock(NetBlock::SEQU);
|
|
bl->append(a1);
|
|
bl->append(st);
|
|
|
|
return bl;
|
|
}
|
|
|
|
if (mux == 0) {
|
|
/* This is a simple assign to a register. There may be a
|
|
part select, so take care that the width is of the
|
|
part, and using the lsb, make sure the correct range
|
|
of bits is assigned. */
|
|
unsigned wid = (msb >= lsb)? (msb-lsb+1) : (lsb-msb+1);
|
|
assert(wid <= reg->pin_count());
|
|
|
|
rv->set_width(wid);
|
|
rv = pad_to_width(rv, wid);
|
|
assert(rv->expr_width() >= wid);
|
|
|
|
cur = new NetAssign(des->local_symbol(path), des, wid, rv);
|
|
unsigned off = reg->sb_to_idx(lsb);
|
|
assert((off+wid) <= reg->pin_count());
|
|
for (unsigned idx = 0 ; idx < wid ; idx += 1)
|
|
connect(cur->pin(idx), reg->pin(idx+off));
|
|
|
|
} else {
|
|
|
|
assert(msb == lsb);
|
|
cur = new NetAssign(des->local_symbol(path), des,
|
|
reg->pin_count(), mux, rv);
|
|
for (unsigned idx = 0 ; idx < reg->pin_count() ; idx += 1)
|
|
connect(cur->pin(idx), reg->pin(idx));
|
|
}
|
|
|
|
|
|
cur->set_line(*this);
|
|
des->add_node(cur);
|
|
|
|
return cur;
|
|
}
|
|
|
|
/*
|
|
* I do not really know how to elaborate mem[x] <= expr, so this
|
|
* method pretends it is a blocking assign and elaborates
|
|
* that. However, I report an error so that the design isn't actually
|
|
* executed by anyone.
|
|
*/
|
|
NetProc* PAssignNB::assign_to_memory_(NetMemory*mem, PExpr*ix,
|
|
Design*des, const string&path) const
|
|
{
|
|
/* Elaborate the r-value expression, ... */
|
|
NetExpr*rv = rval()->elaborate_expr(des, path);
|
|
if (rv == 0)
|
|
return 0;
|
|
|
|
assert(rv);
|
|
rv->set_width(mem->width());
|
|
|
|
/* Elaborate the expression to calculate the index, ... */
|
|
NetExpr*idx = ix->elaborate_expr(des, path);
|
|
assert(idx);
|
|
|
|
/* And connect them together in an assignment NetProc. */
|
|
NetAssignMemNB*am = new NetAssignMemNB(mem, idx, rv);
|
|
am->set_line(*this);
|
|
|
|
return am;
|
|
}
|
|
|
|
/*
|
|
* The l-value of a procedural assignment is a very much constrained
|
|
* expression. To wit, only identifiers, bit selects and part selects
|
|
* are allowed. I therefore can elaborate the l-value by hand, without
|
|
* the help of recursive elaboration.
|
|
*
|
|
* (For now, this does not yet support concatenation in the l-value.)
|
|
*/
|
|
NetProc* PAssignNB::elaborate(Design*des, const string&path) const
|
|
{
|
|
/* Catch the case where the lvalue is a reference to a memory
|
|
item. These are handled differently. */
|
|
do {
|
|
const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
|
|
if (id == 0) break;
|
|
|
|
if (NetMemory*mem = des->find_memory(path+"."+id->name()))
|
|
return assign_to_memory_(mem, id->msb_, des, path);
|
|
|
|
} while(0);
|
|
|
|
|
|
unsigned lsb, msb;
|
|
NetExpr*mux;
|
|
NetNet*reg = elaborate_lval(des, path, msb, lsb, mux);
|
|
if (reg == 0) return 0;
|
|
|
|
assert(rval());
|
|
|
|
/* Elaborate the r-value expression. This generates a
|
|
procedural expression that I attach to the assignment. */
|
|
NetExpr*rv = rval()->elaborate_expr(des, path);
|
|
if (rv == 0)
|
|
return 0;
|
|
|
|
assert(rv);
|
|
|
|
NetAssignNB*cur;
|
|
if (mux == 0) {
|
|
unsigned wid = msb - lsb + 1;
|
|
|
|
rv->set_width(wid);
|
|
rv = pad_to_width(rv, wid);
|
|
assert(wid <= rv->expr_width());
|
|
|
|
cur = new NetAssignNB(des->local_symbol(path), des, wid, rv);
|
|
for (unsigned idx = 0 ; idx < wid ; idx += 1)
|
|
connect(cur->pin(idx), reg->pin(idx+lsb));
|
|
|
|
} else {
|
|
assert(reg->pin_count() == 1);
|
|
cur = new NetAssignNB(des->local_symbol(path), des, 1, mux, rv);
|
|
connect(cur->pin(0), reg->pin(0));
|
|
}
|
|
|
|
unsigned long rise_time, fall_time, decay_time;
|
|
delay_.eval_delays(des, path, rise_time, fall_time, decay_time);
|
|
cur->rise_time(rise_time);
|
|
cur->fall_time(fall_time);
|
|
cur->decay_time(decay_time);
|
|
|
|
|
|
/* All done with this node. mark its line number and check it in. */
|
|
cur->set_line(*this);
|
|
des->add_node(cur);
|
|
return cur;
|
|
}
|
|
|
|
|
|
/*
|
|
* This is the elaboration method for a begin-end block. Try to
|
|
* elaborate the entire block, even if it fails somewhere. This way I
|
|
* get all the error messages out of it. Then, if I detected a failure
|
|
* then pass the failure up.
|
|
*/
|
|
NetProc* PBlock::elaborate(Design*des, const string&path) const
|
|
{
|
|
NetBlock::Type type = (bl_type_==PBlock::BL_PAR)
|
|
? NetBlock::PARA
|
|
: NetBlock::SEQU;
|
|
NetBlock*cur = new NetBlock(type);
|
|
bool fail_flag = false;
|
|
|
|
string npath = name_.length()? (path+"."+name_) : path;
|
|
|
|
// Handle the special case that the block contains only one
|
|
// statement. There is no need to keep the block node.
|
|
if (list_.count() == 1) {
|
|
NetProc*tmp = list_[0]->elaborate(des, npath);
|
|
return tmp;
|
|
}
|
|
|
|
for (unsigned idx = 0 ; idx < list_.count() ; idx += 1) {
|
|
NetProc*tmp = list_[idx]->elaborate(des, npath);
|
|
if (tmp == 0) {
|
|
fail_flag = true;
|
|
continue;
|
|
}
|
|
cur->append(tmp);
|
|
}
|
|
|
|
if (fail_flag) {
|
|
delete cur;
|
|
cur = 0;
|
|
}
|
|
|
|
return cur;
|
|
}
|
|
|
|
/*
|
|
* Elaborate a case statement.
|
|
*/
|
|
NetProc* PCase::elaborate(Design*des, const string&path) const
|
|
{
|
|
NetExpr*expr = expr_->elaborate_expr(des, path);
|
|
if (expr == 0) {
|
|
cerr << get_line() << ": error: Unable to elaborate this case"
|
|
" expression." << endl;
|
|
return 0;
|
|
}
|
|
|
|
unsigned icount = 0;
|
|
for (unsigned idx = 0 ; idx < items_->count() ; idx += 1) {
|
|
PCase::Item*cur = (*items_)[idx];
|
|
|
|
if (cur->expr.count() == 0)
|
|
icount += 1;
|
|
else
|
|
icount += cur->expr.count();
|
|
}
|
|
|
|
NetCase*res = new NetCase(type_, expr, icount);
|
|
res->set_line(*this);
|
|
|
|
unsigned inum = 0;
|
|
for (unsigned idx = 0 ; idx < items_->count() ; idx += 1) {
|
|
|
|
assert(inum < icount);
|
|
PCase::Item*cur = (*items_)[idx];
|
|
|
|
if (cur->expr.count() == 0) {
|
|
/* If there are no expressions, then this is the
|
|
default case. */
|
|
NetProc*st = 0;
|
|
if (cur->stat)
|
|
st = cur->stat->elaborate(des, path);
|
|
|
|
res->set_case(inum, 0, st);
|
|
inum += 1;
|
|
|
|
} else for (unsigned e = 0; e < cur->expr.count(); e += 1) {
|
|
|
|
/* If there are one or more expressions, then
|
|
iterate over the guard expressions, elaborating
|
|
a separate case for each. (Yes, the statement
|
|
will be elaborated again for each.) */
|
|
NetExpr*gu = 0;
|
|
NetProc*st = 0;
|
|
assert(cur->expr[e]);
|
|
gu = cur->expr[e]->elaborate_expr(des, path);
|
|
|
|
if (cur->stat)
|
|
st = cur->stat->elaborate(des, path);
|
|
|
|
res->set_case(inum, gu, st);
|
|
inum += 1;
|
|
}
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
NetProc* PCondit::elaborate(Design*des, const string&path) const
|
|
{
|
|
// Elaborate and try to evaluate the conditional expression.
|
|
NetExpr*expr = expr_->elaborate_expr(des, path);
|
|
if (expr == 0) {
|
|
cerr << get_line() << ": error: Unable to elaborate"
|
|
" condition expression." << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
NetExpr*tmp = expr->eval_tree();
|
|
if (tmp) {
|
|
delete expr;
|
|
expr = tmp;
|
|
}
|
|
|
|
// If the condition of the conditional statement is constant,
|
|
// then look at the value and elaborate either the if statement
|
|
// or the else statement. I don't need both. If there is no
|
|
// else_ statement, the use an empty block as a noop.
|
|
if (NetEConst*ce = dynamic_cast<NetEConst*>(expr)) {
|
|
verinum val = ce->value();
|
|
delete expr;
|
|
if (val[0] == verinum::V1)
|
|
return if_->elaborate(des, path);
|
|
else if (else_)
|
|
return else_->elaborate(des, path);
|
|
else
|
|
return new NetBlock(NetBlock::SEQU);
|
|
}
|
|
|
|
// If the condition expression is more then 1 bits, then
|
|
// generate a comparison operator to get the result down to
|
|
// one bit. Turn <e> into <e> != 0;
|
|
|
|
if (expr->expr_width() < 1) {
|
|
cerr << get_line() << ": internal error: "
|
|
"incomprehensible expression width (0)." << endl;
|
|
return 0;
|
|
}
|
|
|
|
if (! expr->set_width(1)) {
|
|
assert(expr->expr_width() > 1);
|
|
verinum zero (verinum::V0, expr->expr_width());
|
|
NetEConst*ezero = new NetEConst(zero);
|
|
ezero->set_width(expr->expr_width());
|
|
NetEBComp*cmp = new NetEBComp('n', expr, ezero);
|
|
expr = cmp;
|
|
}
|
|
|
|
// Well, I actually need to generate code to handle the
|
|
// conditional, so elaborate.
|
|
NetProc*i = if_? if_->elaborate(des, path) : 0;
|
|
NetProc*e = else_? else_->elaborate(des, path) : 0;
|
|
|
|
NetCondit*res = new NetCondit(expr, i, e);
|
|
return res;
|
|
}
|
|
|
|
NetProc* PCallTask::elaborate(Design*des, const string&path) const
|
|
{
|
|
if (name_[0] == '$')
|
|
return elaborate_sys(des, path);
|
|
else
|
|
return elaborate_usr(des, path);
|
|
}
|
|
|
|
/*
|
|
* A call to a system task involves elaborating all the parameters,
|
|
* then passing the list to the NetSTask object.
|
|
*/
|
|
NetProc* PCallTask::elaborate_sys(Design*des, const string&path) const
|
|
{
|
|
svector<NetExpr*>eparms (nparms());
|
|
|
|
for (unsigned idx = 0 ; idx < nparms() ; idx += 1) {
|
|
PExpr*ex = parm(idx);
|
|
eparms[idx] = ex? ex->elaborate_expr(des, path) : 0;
|
|
}
|
|
|
|
NetSTask*cur = new NetSTask(name(), eparms);
|
|
return cur;
|
|
}
|
|
|
|
/*
|
|
* A call to a user defined task is different from a call to a system
|
|
* task because a user task in a netlist has no parameters: the
|
|
* assignments are done by the calling thread. For example:
|
|
*
|
|
* task foo;
|
|
* input a;
|
|
* output b;
|
|
* [...]
|
|
* endtask;
|
|
*
|
|
* [...] foo(x, y);
|
|
*
|
|
* is really:
|
|
*
|
|
* task foo;
|
|
* reg a;
|
|
* reg b;
|
|
* [...]
|
|
* endtask;
|
|
*
|
|
* [...]
|
|
* begin
|
|
* a = x;
|
|
* foo;
|
|
* y = b;
|
|
* end
|
|
*/
|
|
NetProc* PCallTask::elaborate_usr(Design*des, const string&path) const
|
|
{
|
|
NetTaskDef*def = des->find_task(path, name_);
|
|
if (def == 0) {
|
|
cerr << get_line() << ": error: Enable of unknown task ``" <<
|
|
path << "." << name_ << "''." << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
if (nparms() != def->port_count()) {
|
|
cerr << get_line() << ": error: Port count mismatch in call to ``"
|
|
<< name_ << "''." << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
|
|
NetUTask*cur;
|
|
|
|
/* Handle tasks with no parameters specially. There is no need
|
|
to make a sequential block to hold the generated code. */
|
|
if (nparms() == 0) {
|
|
cur = new NetUTask(def);
|
|
return cur;
|
|
}
|
|
|
|
NetBlock*block = new NetBlock(NetBlock::SEQU);
|
|
|
|
/* Generate assignment statement statements for the input and
|
|
INOUT ports of the task. These are managed by writing
|
|
assignments with the task port the l-value and the passed
|
|
expression the r-value. */
|
|
for (unsigned idx = 0 ; idx < nparms() ; idx += 1) {
|
|
|
|
NetNet*port = def->port(idx);
|
|
assert(port->port_type() != NetNet::NOT_A_PORT);
|
|
if (port->port_type() == NetNet::POUTPUT)
|
|
continue;
|
|
|
|
NetExpr*rv = parms_[idx]->elaborate_expr(des, path);
|
|
NetAssign*pr = new NetAssign("@", des, port->pin_count(), rv);
|
|
for (unsigned pi = 0 ; pi < port->pin_count() ; pi += 1)
|
|
connect(port->pin(pi), pr->pin(pi));
|
|
des->add_node(pr);
|
|
block->append(pr);
|
|
}
|
|
|
|
/* Generate the task call proper... */
|
|
cur = new NetUTask(def);
|
|
block->append(cur);
|
|
|
|
/* Generate assignment statement statements for the output and
|
|
INOUT ports of the task. The l-value in this case is the
|
|
expression passed as a parameter, and the r-value is the
|
|
port to be copied out. */
|
|
for (unsigned idx = 0 ; idx < nparms() ; idx += 1) {
|
|
|
|
NetNet*port = def->port(idx);
|
|
assert(port->port_type() != NetNet::NOT_A_PORT);
|
|
if (port->port_type() == NetNet::PINPUT)
|
|
continue;
|
|
|
|
/* Elaborate the parameter expression as a net so that
|
|
it can be used as an l-value. Then check that the
|
|
parameter width match up. */
|
|
NetNet*val = parms_[idx]->elaborate_net(des, path);
|
|
assert(val);
|
|
|
|
|
|
/* Make an expression out of the actual task port. If
|
|
the port is smaller then the expression to redeive
|
|
the result, then expand the port by padding with
|
|
zeros. */
|
|
NetESignal*sig = new NetESignal(port);
|
|
NetExpr*pexp = sig;
|
|
if (sig->expr_width() < val->pin_count()) {
|
|
unsigned cwid = val->pin_count()-sig->expr_width();
|
|
verinum pad (verinum::V0, cwid);
|
|
NetEConst*cp = new NetEConst(pad);
|
|
cp->set_width(cwid);
|
|
|
|
NetEConcat*con = new NetEConcat(2);
|
|
con->set(0, cp);
|
|
con->set(1, sig);
|
|
con->set_width(val->pin_count());
|
|
pexp = con;
|
|
}
|
|
|
|
|
|
/* Generate the assignment statement. */
|
|
NetAssign*ass = new NetAssign("@", des, val->pin_count(), pexp);
|
|
for (unsigned pi = 0 ; pi < val->pin_count() ; pi += 1)
|
|
connect(val->pin(pi), ass->pin(pi));
|
|
|
|
des->add_node(sig);
|
|
des->add_node(ass);
|
|
block->append(ass);
|
|
}
|
|
|
|
return block;
|
|
}
|
|
|
|
NetProc* PDelayStatement::elaborate(Design*des, const string&path) const
|
|
{
|
|
verinum*num = delay_->eval_const(des, path);
|
|
if (num == 0) {
|
|
cerr << get_line() << ": sorry: delay expression "
|
|
"must be constant." << endl;
|
|
return 0;
|
|
}
|
|
assert(num);
|
|
|
|
unsigned long val = num->as_ulong();
|
|
if (statement_)
|
|
return new NetPDelay(val, statement_->elaborate(des, path));
|
|
else
|
|
return new NetPDelay(val, 0);
|
|
}
|
|
|
|
/*
|
|
* An event statement gets elaborated as a gate net that drives a
|
|
* special node, the NetPEvent. The NetPEvent is also a NetProc class
|
|
* because execution flows through it. Thus, the NetPEvent connects
|
|
* the structural and the behavioral.
|
|
*
|
|
* Note that it is possible for the statement_ pointer to be 0. This
|
|
* happens when the source has something like "@(E) ;". Note the null
|
|
* statement.
|
|
*/
|
|
NetProc* PEventStatement::elaborate_st(Design*des, const string&path,
|
|
NetProc*enet) const
|
|
{
|
|
|
|
/* Create a single NetPEvent, and a unique NetNEvent for each
|
|
conjuctive event. An NetNEvent can have many pins only if
|
|
it is an ANYEDGE detector. Otherwise, only connect to the
|
|
least significant bit of the expression. */
|
|
|
|
NetPEvent*pe = new NetPEvent(des->local_symbol(path), enet);
|
|
for (unsigned idx = 0 ; idx < expr_.count() ; idx += 1) {
|
|
NetNet*expr = expr_[idx]->expr()->elaborate_net(des, path);
|
|
if (expr == 0) {
|
|
expr_[0]->dump(cerr);
|
|
cerr << endl;
|
|
des->errors += 1;
|
|
continue;
|
|
}
|
|
assert(expr);
|
|
|
|
unsigned pins = (expr_[idx]->type() == NetNEvent::ANYEDGE)
|
|
? expr->pin_count() : 1;
|
|
NetNEvent*ne = new NetNEvent(des->local_symbol(path),
|
|
pins, expr_[idx]->type(), pe);
|
|
|
|
for (unsigned p = 0 ; p < pins ; p += 1)
|
|
connect(ne->pin(p), expr->pin(p));
|
|
|
|
des->add_node(ne);
|
|
}
|
|
|
|
return pe;
|
|
}
|
|
|
|
NetProc* PEventStatement::elaborate(Design*des, const string&path) const
|
|
{
|
|
NetProc*enet = 0;
|
|
if (statement_) {
|
|
enet = statement_->elaborate(des, path);
|
|
if (enet == 0)
|
|
return 0;
|
|
}
|
|
|
|
return elaborate_st(des, path, enet);
|
|
}
|
|
|
|
/*
|
|
* Forever statements are represented directly in the netlist. It is
|
|
* theoretically possible to use a while structure with a constant
|
|
* expression to represent the loop, but why complicate the code
|
|
* generators so?
|
|
*/
|
|
NetProc* PForever::elaborate(Design*des, const string&path) const
|
|
{
|
|
NetProc*stat = statement_->elaborate(des, path);
|
|
if (stat == 0) return 0;
|
|
|
|
NetForever*proc = new NetForever(stat);
|
|
return proc;
|
|
}
|
|
|
|
/*
|
|
* elaborate the for loop as the equivalent while loop. This eases the
|
|
* task for the target code generator. The structure is:
|
|
*
|
|
* begin : top
|
|
* name1_ = expr1_;
|
|
* while (cond_) begin : body
|
|
* statement_;
|
|
* name2_ = expr2_;
|
|
* end
|
|
* end
|
|
*/
|
|
NetProc* PForStatement::elaborate(Design*des, const string&path) const
|
|
{
|
|
const PEIdent*id1 = dynamic_cast<const PEIdent*>(name1_);
|
|
assert(id1);
|
|
const PEIdent*id2 = dynamic_cast<const PEIdent*>(name2_);
|
|
assert(id2);
|
|
|
|
NetBlock*top = new NetBlock(NetBlock::SEQU);
|
|
|
|
/* make the expression, and later the initial assignment to
|
|
the condition variable. The statement in the for loop is
|
|
very specifically an assignment. */
|
|
NetNet*sig = des->find_signal(path, id1->name());
|
|
if (sig == 0) {
|
|
cerr << id1->get_line() << ": register ``" << id1->name()
|
|
<< "'' unknown in this context." << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
assert(sig);
|
|
NetAssign*init = new NetAssign("@for-assign", des, sig->pin_count(),
|
|
expr1_->elaborate_expr(des, path));
|
|
for (unsigned idx = 0 ; idx < init->pin_count() ; idx += 1)
|
|
connect(init->pin(idx), sig->pin(idx));
|
|
|
|
top->append(init);
|
|
|
|
NetBlock*body = new NetBlock(NetBlock::SEQU);
|
|
|
|
/* Elaborate the statement that is contained in the for
|
|
loop. If there is an error, this will return 0 and I should
|
|
skip the append. No need to worry, the error has been
|
|
reported so it's OK that the netlist is bogus. */
|
|
NetProc*tmp = statement_->elaborate(des, path);
|
|
if (tmp)
|
|
body->append(tmp);
|
|
|
|
|
|
/* Elaborate the increment assignment statement at the end of
|
|
the for loop. This is also a very specific assignment
|
|
statement. Put this into the "body" block. */
|
|
sig = des->find_signal(path, id2->name());
|
|
assert(sig);
|
|
NetAssign*step = new NetAssign("@for-assign", des, sig->pin_count(),
|
|
expr2_->elaborate_expr(des, path));
|
|
for (unsigned idx = 0 ; idx < step->pin_count() ; idx += 1)
|
|
connect(step->pin(idx), sig->pin(idx));
|
|
|
|
body->append(step);
|
|
|
|
|
|
/* Elaborate the condition expression. Try to evaluate it too,
|
|
in case it is a constant. This is an interesting case
|
|
worthy of a warning. */
|
|
NetExpr*ce = cond_->elaborate_expr(des, path);
|
|
if (NetExpr*tmp = ce->eval_tree()) {
|
|
if (dynamic_cast<NetEConst*>(tmp))
|
|
cerr << get_line() << ": warning: condition expression "
|
|
"is constant." << endl;
|
|
|
|
ce = tmp;
|
|
}
|
|
|
|
|
|
/* All done, build up the loop. */
|
|
|
|
NetWhile*loop = new NetWhile(ce, body);
|
|
top->append(loop);
|
|
return top;
|
|
}
|
|
|
|
/*
|
|
* Elaborating function definitions takes 2 passes. The first creates
|
|
* the NetFuncDef object and attaches the ports to it. The second pass
|
|
* (elaborate_2) elaborates the statement that is contained
|
|
* within. These passes are needed because the statement may invoke
|
|
* the function itself (or other functions) so can't be elaborated
|
|
* until all the functions are partially elaborated.
|
|
*/
|
|
void PFunction::elaborate_1(Design*des, const string&path) const
|
|
{
|
|
/* Translate the wires that are ports to NetNet pointers by
|
|
presuming that the name is already elaborated, and look it
|
|
up in the design. Then save that pointer for later use by
|
|
calls to the task. (Remember, the task itself does not need
|
|
these ports.) */
|
|
svector<NetNet*>ports (ports_? ports_->count()+1 : 1);
|
|
ports[0] = des->find_signal(path, path);
|
|
for (unsigned idx = 0 ; idx < ports_->count() ; idx += 1) {
|
|
NetNet*tmp = des->find_signal(path, (*ports_)[idx]->name());
|
|
|
|
ports[idx+1] = tmp;
|
|
}
|
|
|
|
NetFuncDef*def = new NetFuncDef(path, ports);
|
|
des->add_function(path, def);
|
|
}
|
|
|
|
void PFunction::elaborate_2(Design*des, const string&path) const
|
|
{
|
|
NetFuncDef*def = des->find_function(path);
|
|
assert(def);
|
|
|
|
NetProc*st = statement_->elaborate(des, path);
|
|
if (st == 0) {
|
|
cerr << statement_->get_line() << ": error: Unable to elaborate "
|
|
"statement in function " << path << "." << endl;
|
|
des->errors += 1;
|
|
return;
|
|
}
|
|
|
|
def->set_proc(st);
|
|
}
|
|
|
|
NetProc* PRepeat::elaborate(Design*des, const string&path) const
|
|
{
|
|
NetExpr*expr = expr_->elaborate_expr(des, path);
|
|
if (expr == 0) {
|
|
cerr << get_line() << ": Unable to elaborate"
|
|
" repeat expression." << endl;
|
|
des->errors += 1;
|
|
return 0;
|
|
}
|
|
NetExpr*tmp = expr->eval_tree();
|
|
if (tmp) {
|
|
delete expr;
|
|
expr = tmp;
|
|
}
|
|
|
|
NetProc*stat = statement_->elaborate(des, path);
|
|
if (stat == 0) return 0;
|
|
|
|
// If the expression is a constant, handle certain special
|
|
// iteration counts.
|
|
if (NetEConst*ce = dynamic_cast<NetEConst*>(expr)) {
|
|
verinum val = ce->value();
|
|
switch (val.as_ulong()) {
|
|
case 0:
|
|
delete expr;
|
|
delete stat;
|
|
return new NetBlock(NetBlock::SEQU);
|
|
case 1:
|
|
delete expr;
|
|
return stat;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
NetRepeat*proc = new NetRepeat(expr, stat);
|
|
return proc;
|
|
}
|
|
|
|
/*
|
|
* A task definition is elaborated by elaborating the statement that
|
|
* it contains, and connecting its ports to NetNet objects. The
|
|
* netlist doesn't really need the array of parameters once elaboration
|
|
* is complete, but this is the best place to store them.
|
|
*/
|
|
void PTask::elaborate_1(Design*des, const string&path) const
|
|
{
|
|
/* Translate the wires that are ports to NetNet pointers by
|
|
presuming that the name is already elaborated, and look it
|
|
up in the design. Then save that pointer for later use by
|
|
calls to the task. (Remember, the task itself does not need
|
|
these ports.) */
|
|
svector<NetNet*>ports (ports_? ports_->count() : 0);
|
|
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
|
|
NetNet*tmp = des->find_signal(path, (*ports_)[idx]->name());
|
|
|
|
ports[idx] = tmp;
|
|
}
|
|
|
|
NetTaskDef*def = new NetTaskDef(path, ports);
|
|
des->add_task(path, def);
|
|
}
|
|
|
|
void PTask::elaborate_2(Design*des, const string&path) const
|
|
{
|
|
NetTaskDef*def = des->find_task(path);
|
|
assert(def);
|
|
|
|
NetProc*st;
|
|
if (statement_ == 0) {
|
|
cerr << get_line() << ": warning: task has no statement." << endl;
|
|
st = new NetBlock(NetBlock::SEQU);
|
|
|
|
} else {
|
|
|
|
st = statement_->elaborate(des, path);
|
|
if (st == 0) {
|
|
cerr << statement_->get_line() << ": Unable to elaborate "
|
|
"statement in task " << path << " at " << get_line()
|
|
<< "." << endl;
|
|
return;
|
|
}
|
|
}
|
|
|
|
def->set_proc(st);
|
|
}
|
|
|
|
/*
|
|
* The while loop is fairly directly represented in the netlist.
|
|
*/
|
|
NetProc* PWhile::elaborate(Design*des, const string&path) const
|
|
{
|
|
NetWhile*loop = new NetWhile(cond_->elaborate_expr(des, path),
|
|
statement_->elaborate(des, path));
|
|
return loop;
|
|
}
|
|
|
|
bool Module::elaborate(Design*des, const string&path, svector<PExpr*>*overrides_) const
|
|
{
|
|
bool result_flag = true;
|
|
|
|
// Generate all the parameters that this instance of this
|
|
// module introduce to the design. This needs to be done in
|
|
// two passes. The first pass marks the parameter names as
|
|
// available so that they can be discovered when the second
|
|
// pass references them during elaboration.
|
|
typedef map<string,PExpr*>::const_iterator mparm_it_t;
|
|
|
|
// So this loop elaborates the parameters, ...
|
|
for (mparm_it_t cur = parameters.begin()
|
|
; cur != parameters.end() ; cur ++) {
|
|
string pname = path + "." + (*cur).first;
|
|
des->set_parameter(pname, new NetEParam);
|
|
}
|
|
|
|
// and this loop elaborates the expressions.
|
|
for (mparm_it_t cur = parameters.begin()
|
|
; cur != parameters.end() ; cur ++) {
|
|
string pname = path + "." + (*cur).first;
|
|
NetExpr*expr = (*cur).second->elaborate_expr(des, path);
|
|
des->set_parameter(pname, expr);
|
|
}
|
|
|
|
// Override parameters
|
|
// FIXME: need to check if too many overrides given
|
|
// FIXME: need to release the replaced expression.
|
|
|
|
if (overrides_) {
|
|
list<string>::const_iterator cur = param_names.begin();
|
|
for (unsigned idx = 0 ; idx < overrides_->count(); idx += 1, cur++) {
|
|
string pname = path + "." + (*cur);
|
|
NetExpr*expr = (*overrides_)[idx]->elaborate_expr(des, path);
|
|
des->set_parameter(pname, expr);
|
|
}
|
|
}
|
|
|
|
// Finally, evaluate the parameter value. This step collapses
|
|
// the parameters to NetEConst values.
|
|
for (mparm_it_t cur = parameters.begin()
|
|
; cur != parameters.end() ; cur ++) {
|
|
|
|
// Get the NetExpr for the parameter.
|
|
string pname = path + "." + (*cur).first;
|
|
const NetExpr*expr = des->find_parameter(path, (*cur).first);
|
|
assert(expr);
|
|
|
|
// If it's already a NetEConst, then this parameter is done.
|
|
if (dynamic_cast<const NetEConst*>(expr))
|
|
continue;
|
|
|
|
// Get a non-constant copy of the expression to evaluate...
|
|
NetExpr*nexpr = expr->dup_expr();
|
|
if (nexpr == 0) {
|
|
cerr << (*cur).second->get_line() << ": internal error: "
|
|
"unable to dup expression: " << *expr << endl;
|
|
des->errors += 1;
|
|
continue;
|
|
}
|
|
|
|
// Try to evaluate the expression.
|
|
nexpr = nexpr->eval_tree();
|
|
if (nexpr == 0) {
|
|
cerr << (*cur).second->get_line() << ": internal error: "
|
|
"unable to evaluate parm expression: " <<
|
|
*expr << endl;
|
|
des->errors += 1;
|
|
continue;
|
|
}
|
|
|
|
// The evaluate worked, replace the old expression with
|
|
// this constant value.
|
|
assert(nexpr);
|
|
des->set_parameter(pname, nexpr);
|
|
}
|
|
|
|
// Get all the explicitly declared wires of the module and
|
|
// start the signals list with them.
|
|
const list<PWire*>&wl = get_wires();
|
|
|
|
for (list<PWire*>::const_iterator wt = wl.begin()
|
|
; wt != wl.end()
|
|
; wt ++ ) {
|
|
|
|
(*wt)->elaborate(des, path);
|
|
}
|
|
|
|
// Elaborate functions.
|
|
typedef map<string,PFunction*>::const_iterator mfunc_it_t;
|
|
|
|
for (mfunc_it_t cur = funcs_.begin()
|
|
; cur != funcs_.end() ; cur ++) {
|
|
string pname = path + "." + (*cur).first;
|
|
(*cur).second->elaborate_1(des, pname);
|
|
}
|
|
|
|
for (mfunc_it_t cur = funcs_.begin()
|
|
; cur != funcs_.end() ; cur ++) {
|
|
string pname = path + "." + (*cur).first;
|
|
(*cur).second->elaborate_2(des, pname);
|
|
}
|
|
|
|
// Elaborate the task definitions. This is done before the
|
|
// behaviors so that task calls may reference these, and after
|
|
// the signals so that the tasks can reference them.
|
|
typedef map<string,PTask*>::const_iterator mtask_it_t;
|
|
|
|
for (mtask_it_t cur = tasks_.begin()
|
|
; cur != tasks_.end() ; cur ++) {
|
|
string pname = path + "." + (*cur).first;
|
|
(*cur).second->elaborate_1(des, pname);
|
|
}
|
|
|
|
for (mtask_it_t cur = tasks_.begin()
|
|
; cur != tasks_.end() ; cur ++) {
|
|
string pname = path + "." + (*cur).first;
|
|
(*cur).second->elaborate_2(des, pname);
|
|
}
|
|
|
|
// Get all the gates of the module and elaborate them by
|
|
// connecting them to the signals. The gate may be simple or
|
|
// complex.
|
|
const list<PGate*>&gl = get_gates();
|
|
|
|
for (list<PGate*>::const_iterator gt = gl.begin()
|
|
; gt != gl.end()
|
|
; gt ++ ) {
|
|
|
|
(*gt)->elaborate(des, path);
|
|
}
|
|
|
|
// Elaborate the behaviors, making processes out of them.
|
|
const list<PProcess*>&sl = get_behaviors();
|
|
|
|
for (list<PProcess*>::const_iterator st = sl.begin()
|
|
; st != sl.end()
|
|
; st ++ ) {
|
|
|
|
NetProc*cur = (*st)->statement()->elaborate(des, path);
|
|
if (cur == 0) {
|
|
cerr << (*st)->get_line() << ": error: Elaboration "
|
|
"failed for this process." << endl;
|
|
result_flag = false;
|
|
continue;
|
|
}
|
|
|
|
NetProcTop*top;
|
|
switch ((*st)->type()) {
|
|
case PProcess::PR_INITIAL:
|
|
top = new NetProcTop(NetProcTop::KINITIAL, cur);
|
|
break;
|
|
case PProcess::PR_ALWAYS:
|
|
top = new NetProcTop(NetProcTop::KALWAYS, cur);
|
|
break;
|
|
}
|
|
|
|
top->set_line(*(*st));
|
|
des->add_process(top);
|
|
}
|
|
|
|
return result_flag;
|
|
}
|
|
|
|
Design* elaborate(const map<string,Module*>&modules,
|
|
const map<string,PUdp*>&primitives,
|
|
const string&root)
|
|
{
|
|
// Look for the root module in the list.
|
|
map<string,Module*>::const_iterator mod = modules.find(root);
|
|
if (mod == modules.end())
|
|
return 0;
|
|
|
|
Module*rmod = (*mod).second;
|
|
|
|
// This is the output design. I fill it in as I scan the root
|
|
// module and elaborate what I find.
|
|
Design*des = new Design;
|
|
|
|
modlist = &modules;
|
|
udplist = &primitives;
|
|
bool rc = rmod->elaborate(des, root, (svector<PExpr*>*)0);
|
|
modlist = 0;
|
|
udplist = 0;
|
|
|
|
if (rc == false) {
|
|
delete des;
|
|
des = 0;
|
|
}
|
|
return des;
|
|
}
|
|
|
|
|
|
/*
|
|
* $Log: elaborate.cc,v $
|
|
* Revision 1.111 1999/10/07 05:25:33 steve
|
|
* Add non-const bit select in l-value of assignment.
|
|
*
|
|
* Revision 1.110 1999/10/06 00:39:00 steve
|
|
* == and != connected to the wrong pins of the compare.
|
|
*
|
|
* Revision 1.109 1999/10/05 06:19:46 steve
|
|
* Add support for reduction NOR.
|
|
*
|
|
* Revision 1.108 1999/10/05 02:00:06 steve
|
|
* sorry message for non-constant l-value bit select.
|
|
*
|
|
* Revision 1.107 1999/09/30 21:28:34 steve
|
|
* Handle mutual reference of tasks by elaborating
|
|
* task definitions in two passes, like functions.
|
|
*
|
|
* Revision 1.106 1999/09/30 17:22:33 steve
|
|
* catch non-constant delays as unsupported.
|
|
*
|
|
* Revision 1.105 1999/09/30 02:43:02 steve
|
|
* Elaborate ~^ and ~| operators.
|
|
*
|
|
* Revision 1.104 1999/09/30 00:48:50 steve
|
|
* Cope with errors during ternary operator elaboration.
|
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*
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* Revision 1.103 1999/09/29 22:57:10 steve
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* Move code to elab_expr.cc
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*
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* Revision 1.102 1999/09/29 18:36:03 steve
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* Full case support
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*
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* Revision 1.101 1999/09/29 00:42:50 steve
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* Allow expanding of additive operators.
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*
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* Revision 1.100 1999/09/25 02:57:30 steve
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* Parse system function calls.
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*
|
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* Revision 1.99 1999/09/23 03:56:57 steve
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* Support shift operators.
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*
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* Revision 1.98 1999/09/23 02:28:27 steve
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* internal error message for funky comparison width.
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*
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* Revision 1.97 1999/09/23 00:21:54 steve
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* Move set_width methods into a single file,
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* Add the NetEBLogic class for logic expressions,
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* Fix error setting with of && in if statements.
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*
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* Revision 1.96 1999/09/22 21:25:42 steve
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* Expand bits in delayed assignments.
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*
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* Revision 1.95 1999/09/22 04:30:04 steve
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* Parse and elaborate named for/join blocks.
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*
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* Revision 1.94 1999/09/22 02:00:48 steve
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* assignment with blocking event delay.
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*
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* Revision 1.93 1999/09/20 02:21:10 steve
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* Elaborate parameters in phases.
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*
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* Revision 1.92 1999/09/18 22:23:50 steve
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* Match bit widths comming out of task output ports.
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*
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* Revision 1.91 1999/09/18 02:51:35 steve
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* report non-constant part select expressions.
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*
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* Revision 1.90 1999/09/18 01:53:08 steve
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* Detect constant lessthen-equal expressions.
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*
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* Revision 1.89 1999/09/17 02:06:25 steve
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* Handle unconnected module ports.
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*
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* Revision 1.88 1999/09/16 04:18:15 steve
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* elaborate concatenation repeats.
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*
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* Revision 1.87 1999/09/16 00:33:45 steve
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* Handle implicit !=0 in if statements.
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*
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* Revision 1.86 1999/09/15 04:17:52 steve
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* separate assign lval elaboration for error checking.
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*
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* Revision 1.85 1999/09/15 01:55:06 steve
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* Elaborate non-blocking assignment to memories.
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*
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|
* Revision 1.84 1999/09/14 01:50:52 steve
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* implicitly declare wires if needed.
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*
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* Revision 1.83 1999/09/13 03:10:59 steve
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* Clarify msb/lsb in context of netlist. Properly
|
|
* handle part selects in lval and rval of expressions,
|
|
* and document where the least significant bit goes
|
|
* in NetNet objects.
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*
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* Revision 1.82 1999/09/12 01:16:51 steve
|
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* Pad r-values in certain assignments.
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*
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|
* Revision 1.81 1999/09/10 04:04:06 steve
|
|
* Add ternary elaboration.
|
|
*
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* Revision 1.80 1999/09/08 04:05:30 steve
|
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* Allow assign to not match rvalue width.
|
|
*
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* Revision 1.79 1999/09/08 02:24:39 steve
|
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* Empty conditionals (pmonta@imedia.com)
|
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*
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|
* Revision 1.78 1999/09/04 19:11:46 steve
|
|
* Add support for delayed non-blocking assignments.
|
|
*
|
|
* Revision 1.77 1999/09/03 04:28:38 steve
|
|
* elaborate the binary plus operator.
|
|
*
|
|
* Revision 1.76 1999/09/02 01:59:27 steve
|
|
* Parse non-blocking assignment delays.
|
|
*
|
|
* Revision 1.75 1999/09/01 20:46:19 steve
|
|
* Handle recursive functions and arbitrary function
|
|
* references to other functions, properly pass
|
|
* function parameters and save function results.
|
|
*
|
|
* Revision 1.74 1999/08/31 22:38:29 steve
|
|
* Elaborate and emit to vvm procedural functions.
|
|
*
|
|
* Revision 1.73 1999/08/25 22:22:41 steve
|
|
* elaborate some aspects of functions.
|
|
*
|
|
* Revision 1.72 1999/08/23 16:48:39 steve
|
|
* Parameter overrides support from Peter Monta
|
|
* AND and XOR support wide expressions.
|
|
*
|
|
* Revision 1.71 1999/08/18 04:00:02 steve
|
|
* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
|
|
*
|
|
* Revision 1.70 1999/08/08 20:06:06 steve
|
|
* Uninitialized low and high indices for single gate syntax
|
|
*
|
|
* Revision 1.69 1999/08/06 04:05:28 steve
|
|
* Handle scope of parameters.
|
|
*
|
|
* Revision 1.68 1999/08/05 04:58:57 steve
|
|
* Allow integers as register lvalues.
|
|
*
|
|
* Revision 1.67 1999/08/04 02:13:02 steve
|
|
* Elaborate module ports that are concatenations of
|
|
* module signals.
|
|
*
|
|
* Revision 1.66 1999/08/03 04:14:49 steve
|
|
* Parse into pform arbitrarily complex module
|
|
* port declarations.
|
|
*
|
|
* Revision 1.65 1999/08/01 21:48:11 steve
|
|
* set width of procedural r-values when then
|
|
* l-value is a memory word.
|
|
*
|
|
* Revision 1.64 1999/08/01 21:18:55 steve
|
|
* elaborate rise/fall/decay for continuous assign.
|
|
*
|
|
* Revision 1.63 1999/08/01 16:34:50 steve
|
|
* Parse and elaborate rise/fall/decay times
|
|
* for gates, and handle the rules for partial
|
|
* lists of times.
|
|
*
|
|
* Revision 1.62 1999/07/31 03:16:54 steve
|
|
* move binary operators to derived classes.
|
|
*
|
|
* Revision 1.61 1999/07/28 03:46:57 steve
|
|
* Handle no ports at all for tasks.
|
|
*
|
|
* Revision 1.60 1999/07/24 19:19:06 steve
|
|
* Add support for task output and inout ports.
|
|
*
|
|
* Revision 1.59 1999/07/24 02:11:20 steve
|
|
* Elaborate task input ports.
|
|
*
|
|
* Revision 1.58 1999/07/18 21:17:50 steve
|
|
* Add support for CE input to XNF DFF, and do
|
|
* complete cleanup of replaced design nodes.
|
|
*
|
|
* Revision 1.57 1999/07/17 19:50:59 steve
|
|
* netlist support for ternary operator.
|
|
*
|
|
* Revision 1.56 1999/07/17 18:06:02 steve
|
|
* Better handling of bit width of + operators.
|
|
*
|
|
* Revision 1.55 1999/07/17 03:08:31 steve
|
|
* part select in expressions.
|
|
*
|
|
* Revision 1.54 1999/07/13 04:08:26 steve
|
|
* Construct delayed assignment as an equivalent block.
|
|
*
|
|
* Revision 1.53 1999/07/12 00:59:36 steve
|
|
* procedural blocking assignment delays.
|
|
*
|
|
* Revision 1.52 1999/07/10 03:00:05 steve
|
|
* Proper initialization of registers.
|
|
*
|
|
* Revision 1.51 1999/07/10 02:19:26 steve
|
|
* Support concatenate in l-values.
|
|
*
|
|
* Revision 1.50 1999/07/03 02:12:51 steve
|
|
* Elaborate user defined tasks.
|
|
*
|
|
* Revision 1.49 1999/06/24 04:45:29 steve
|
|
* Elaborate wide structoral bitwise OR.
|
|
*
|
|
* Revision 1.48 1999/06/24 04:24:18 steve
|
|
* Handle expression widths for EEE and NEE operators,
|
|
* add named blocks and scope handling,
|
|
* add registers declared in named blocks.
|
|
*
|
|
* Revision 1.47 1999/06/19 21:06:16 steve
|
|
* Elaborate and supprort to vvm the forever
|
|
* and repeat statements.
|
|
*
|
|
* Revision 1.46 1999/06/17 05:34:42 steve
|
|
* Clean up interface of the PWire class,
|
|
* Properly match wire ranges.
|
|
*
|
|
* Revision 1.45 1999/06/15 05:38:39 steve
|
|
* Support case expression lists.
|
|
*
|
|
* Revision 1.44 1999/06/15 03:44:53 steve
|
|
* Get rid of the STL vector template.
|
|
*
|
|
* Revision 1.43 1999/06/13 23:51:16 steve
|
|
* l-value part select for procedural assignments.
|
|
*
|
|
* Revision 1.42 1999/06/13 16:30:06 steve
|
|
* Unify the NetAssign constructors a bit.
|
|
*
|
|
* Revision 1.41 1999/06/13 04:46:54 steve
|
|
* Add part select lvalues to AssignNB.
|
|
*
|
|
* Revision 1.40 1999/06/12 23:16:37 steve
|
|
* Handle part selects as l-values to continuous assign.
|
|
*
|
|
* Revision 1.39 1999/06/10 04:03:53 steve
|
|
* Add support for the Ternary operator,
|
|
* Add support for repeat concatenation,
|
|
* Correct some seg faults cause by elaboration
|
|
* errors,
|
|
* Parse the casex anc casez statements.
|
|
*
|
|
* Revision 1.38 1999/06/09 03:00:06 steve
|
|
* Add support for procedural concatenation expression.
|
|
*
|
|
* Revision 1.37 1999/06/09 00:58:06 steve
|
|
* Support for binary | (Stephen Tell)
|
|
*
|
|
* Revision 1.36 1999/06/07 02:23:31 steve
|
|
* Support non-blocking assignment down to vvm.
|
|
*
|
|
* Revision 1.35 1999/06/06 23:07:43 steve
|
|
* Drop degenerate blocks.
|
|
*
|
|
* Revision 1.34 1999/06/06 20:45:38 steve
|
|
* Add parse and elaboration of non-blocking assignments,
|
|
* Replace list<PCase::Item*> with an svector version,
|
|
* Add integer support.
|
|
*
|
|
* Revision 1.33 1999/06/03 05:16:25 steve
|
|
* Compile time evalutation of constant expressions.
|
|
*
|
|
* Revision 1.32 1999/06/02 15:38:46 steve
|
|
* Line information with nets.
|
|
*
|
|
* Revision 1.31 1999/05/31 15:45:35 steve
|
|
* Fix error message.
|
|
*
|
|
* Revision 1.30 1999/05/30 01:11:46 steve
|
|
* Exressions are trees that can duplicate, and not DAGS.
|
|
*
|
|
* Revision 1.29 1999/05/29 02:36:17 steve
|
|
* module parameter bind by name.
|
|
*
|
|
* Revision 1.28 1999/05/27 04:13:08 steve
|
|
* Handle expression bit widths with non-fatal errors.
|
|
*
|
|
* Revision 1.27 1999/05/20 04:31:45 steve
|
|
* Much expression parsing work,
|
|
* mark continuous assigns with source line info,
|
|
* replace some assertion failures with Sorry messages.
|
|
*
|
|
* Revision 1.26 1999/05/16 05:08:42 steve
|
|
* Redo constant expression detection to happen
|
|
* after parsing.
|
|
*
|
|
* Parse more operators and expressions.
|
|
*
|
|
* Revision 1.25 1999/05/10 00:16:58 steve
|
|
* Parse and elaborate the concatenate operator
|
|
* in structural contexts, Replace vector<PExpr*>
|
|
* and list<PExpr*> with svector<PExpr*>, evaluate
|
|
* constant expressions with parameters, handle
|
|
* memories as lvalues.
|
|
*
|
|
* Parse task declarations, integer types.
|
|
*
|
|
* Revision 1.24 1999/05/05 03:04:46 steve
|
|
* Fix handling of null delay statements.
|
|
*
|
|
* Revision 1.23 1999/05/01 20:43:55 steve
|
|
* Handle wide events, such as @(a) where a has
|
|
* many bits in it.
|
|
*
|
|
* Add to vvm the binary ^ and unary & operators.
|
|
*
|
|
* Dump events a bit more completely.
|
|
*
|
|
* Revision 1.22 1999/05/01 02:57:53 steve
|
|
* Handle much more complex event expressions.
|
|
*/
|
|
|