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Lars-Peter Clausen
c0cf842eb2
The parameter_omit tests have different expectations depending on whether the regression is run in the default Verilog mode or with force SystemVerilog. The old list files modelled this by registering the same tests in both regress-vlg.list and regress-fsv.list. Move the tests to JSON descriptors. Use the existing force-sv override for the forms that are valid SystemVerilog, and keep the implicit type cases as CE in both modes. This also runs the tests through the additional configurations supported by vvp_reg.py, providing better coverage in CI. Signed-off-by: Lars-Peter Clausen <[email protected]>
5 lines
82 B
JSON
5 lines
82 B
JSON
{
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"type" : "CE",
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"source" : "parameter_omit_invalid2.v"
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}
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