mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 03:43:19 +02:00
mjoekhan
9880fb8d5e
Fold in Windows VPI routing for vpip_format_pretty, fix queue method argument elaboration via elaborate_rval_expr, reject class tasks used as expressions cleanly, and update br1005 now that class queues compile. Review follow-up: move vpip_format_pretty to vpip_format.cc with diagnostic return strings, restore NetNet-based queue method elaboration with a separate property path, drop spurious /devel/ from .gitignore, and bump copyright years on touched files. Formatting pass per inline review: brace style for multi-line if bodies, ||/&& at end-of-line continuations, switch/case indentation, single-line if returns, NetNet-based sys_task_method_ again, and aligned extern decls.
40 lines
802 B
Verilog
40 lines
802 B
Verilog
// Regression: queue-typed class properties — push_front/push_back and
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// pop_front/pop_back. (VVP asm must recognize %store/prop/qf/* and
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// %qpop/prop/*; opcode_table must stay lexicographically sorted.)
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). expected %0d, got %0d", `__LINE__, exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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int q[$];
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endclass
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C c;
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int t;
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initial begin
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c = new;
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c.q.push_back(1);
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c.q.push_front(0);
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c.q.push_back(2);
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t = c.q.pop_back();
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`check(t, 32'd2);
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`check(c.q.size(), 32'd2);
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t = c.q.pop_front();
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`check(t, 32'd0);
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`check(c.q[0], 32'd1);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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