36 lines
706 B
Verilog
36 lines
706 B
Verilog
// Regression: queue unique()/unique_index() with predicate.
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module top;
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bit failed = 0;
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`define CHK(cond) if (!(cond)) begin $display("FAILED line %0d", `__LINE__); failed = 1; end
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int q[$];
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int r[$];
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initial begin
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q = '{4, 7, 2, 5, 7, 1, 6, 3, 1};
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r = q.unique() with (item > 2);
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`CHK(r.size == 5);
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`CHK(r[0] == 4);
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`CHK(r[1] == 7);
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`CHK(r[2] == 5);
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`CHK(r[3] == 6);
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`CHK(r[4] == 3);
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r = q.unique_index() with (item > 2);
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`CHK(r.size == 6);
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`CHK(r[0] == 0);
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`CHK(r[1] == 1);
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`CHK(r[2] == 3);
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`CHK(r[3] == 4);
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`CHK(r[4] == 6);
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`CHK(r[5] == 7);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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