25 lines
431 B
Verilog
25 lines
431 B
Verilog
// Regression: queue sum() reduction with expression.
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module top;
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bit failed = 0;
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`define CHK(cond) if (!(cond)) begin $display("FAILED line %0d", `__LINE__); failed = 1; end
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int q[$];
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int s;
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initial begin
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q = '{4, 7, 2, 5};
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s = q.sum() with (item > 3);
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`CHK(s === 3);
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s = q.sum() with (item * 2);
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`CHK(s === 36);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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