29 lines
411 B
Verilog
29 lines
411 B
Verilog
// Regression: queue sum() reduction (integral).
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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int q[$];
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int s;
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initial begin
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q = '{};
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s = q.sum();
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`CHK(s === 0);
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q = '{4, 7, 2};
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s = q.sum();
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`CHK(s === 13);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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