34 lines
599 B
Verilog
34 lines
599 B
Verilog
// Regression: queue sort(), rsort(), shuffle().
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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int q[$];
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int sum0;
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initial begin
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q = '{3, 1, 4, 1, 5};
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q.sort();
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`CHK(q[0] === 1 && q[1] === 1 && q[2] === 3 && q[3] === 4 && q[4] === 5);
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q = '{3, 1, 4};
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q.rsort();
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`CHK(q[0] === 4 && q[1] === 3 && q[2] === 1);
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q = '{10, -2, 7};
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sum0 = q.sum();
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q.shuffle();
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`CHK(q.sum() === sum0);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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