32 lines
514 B
Verilog
32 lines
514 B
Verilog
// Regression: queue reverse() ordering method.
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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int q[$];
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initial begin
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q = '{1, 2, 3, 4};
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q.reverse();
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`CHK(q[0] === 4 && q[1] === 3 && q[2] === 2 && q[3] === 1);
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q = '{99};
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q.reverse();
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`CHK(q[0] === 99);
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q.delete();
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q.reverse();
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`CHK(q.size() === 0);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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