30 lines
563 B
Verilog
30 lines
563 B
Verilog
// Regression: dynamic array unique() and unique_index().
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module top;
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bit failed = 0;
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`define CHK(cond) if (!(cond)) begin $display("FAILED line %0d", `__LINE__); failed = 1; end
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int a[] = '{1, 2, 1, 3, 2};
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int u[$];
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int ix[$];
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initial begin
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u = a.unique();
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`CHK(u.size == 3);
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`CHK(u[0] == 1);
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`CHK(u[1] == 2);
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`CHK(u[2] == 3);
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ix = a.unique_index();
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`CHK(ix.size == 3);
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`CHK(ix[0] == 0);
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`CHK(ix[1] == 1);
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`CHK(ix[2] == 3);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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