25 lines
437 B
Verilog
25 lines
437 B
Verilog
// Regression: dynamic array sum() reduction with expression.
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module top;
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bit failed = 0;
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`define CHK(cond) if (!(cond)) begin $display("FAILED line %0d", `__LINE__); failed = 1; end
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int a[];
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int s;
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initial begin
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a = '{10, -3, 5};
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s = a.sum() with (item > 0);
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`CHK(s === 2);
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s = a.sum() with (item + 1);
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`CHK(s === 15);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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