34 lines
606 B
Verilog
34 lines
606 B
Verilog
// Regression: dynamic array sort(), rsort(), shuffle().
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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int a[];
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int sum0;
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initial begin
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a = '{3, 1, 4, 1, 5};
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a.sort();
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`CHK(a[0] === 1 && a[1] === 1 && a[2] === 3 && a[3] === 4 && a[4] === 5);
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a = '{3, 1, 4};
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a.rsort();
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`CHK(a[0] === 4 && a[1] === 3 && a[2] === 1);
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a = '{10, -2, 7};
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sum0 = a.sum();
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a.shuffle();
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`CHK(a.sum() === sum0);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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