33 lines
539 B
Verilog
33 lines
539 B
Verilog
// Regression: dynamic array reverse() ordering method.
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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int a[];
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initial begin
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a = '{1, 2, 3, 4};
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a.reverse();
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`CHK(a[0] === 4 && a[1] === 3 && a[2] === 2 && a[3] === 1);
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a = new [1];
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a[0] = 42;
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a.reverse();
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`CHK(a[0] === 42);
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a = new [0];
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a.reverse();
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`CHK(a.size() === 0);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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