25 lines
432 B
Verilog
25 lines
432 B
Verilog
// Regression: dynamic array product() reduction (integral).
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module top;
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bit failed = 0;
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`define CHK(cond) if (!(cond)) begin $display("FAILED line %0d", `__LINE__); failed = 1; end
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int a[];
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int p;
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initial begin
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a = '{2, 3, 4};
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p = a.product();
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`CHK(p === 24);
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a = '{-2, 3, 5};
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p = a.product();
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`CHK(p === -30);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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