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https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
24 lines
352 B
Verilog
24 lines
352 B
Verilog
module \esc.mod ;
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\esc.sub \esc.inm (1'b1);
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sub inst();
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endmodule
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module \esc.sub (input wire \esc.port );
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reg \esc.val ;
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reg normal;
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initial begin
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$print_if_found();
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normal = 1'b0;
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\esc.val = 1'b1;
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end
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endmodule
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module sub;
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reg \esc.id ;
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reg normal;
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initial begin
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normal = 1'b1;
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\esc.id = 1'b0;
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end
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endmodule
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