mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
45 lines
988 B
Verilog
45 lines
988 B
Verilog
// When registering a simulation time callback, some simulators interpret
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// the specified time value as relative to the current simulation time. To
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// support this case, define the macro CB_TIME_IS_RELATIVE when compiling
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// this module.
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module main;
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integer val1, val2;
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initial begin
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val1 = 0;
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val2 = 1;
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#1;
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$poke_at_simtime(val1, 1, 10);
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$poke_at_simtime(val2, 2, 10);
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`ifdef CB_TIME_IS_RELATIVE
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#1;
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`endif
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#8;
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if (val1 !== 0) begin
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$display("FAILED -- val1==%0d before delayed poke", val1);
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$finish;
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end
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if (val2 !== 1) begin
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$display("FAILED -- val2==%0d before delayed poke", val2);
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$finish;
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end
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#1;
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if (val1 !== 1) begin
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$display("FAILED -- val1==%0d: poke didn't happen", val1);
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$finish;
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end
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if (val2 !== 2) begin
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$display("FAILED -- val2==%0d: poke didn't happen", val2);
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$finish;
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end
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$display("PASSED");
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$finish(0);
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end
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endmodule // main
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