iverilog/net_nex_output.cc

112 lines
2.8 KiB
C++

/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: net_nex_output.cc,v 1.6 2002/09/17 04:39:20 steve Exp $"
#endif
# include "config.h"
# include <iostream>
# include <cassert>
# include <typeinfo>
# include "netlist.h"
# include "netmisc.h"
void NetProc::nex_output(NexusSet&out)
{
cerr << get_line()
<< ": internal error: NetProc::nex_output not implemented"
<< endl;
}
void NetAssignBase::nex_output(NexusSet&out)
{
NetNet*lsig = lval_->sig();
assert(lsig);
assert(lval_->more == 0);
for (unsigned idx = 0 ; idx < lval_->lwidth() ; idx += 1) {
unsigned off = lval_->get_loff() + idx;
out.add(lsig->pin(off).nexus());
}
}
void NetBlock::nex_output(NexusSet&out)
{
if (last_ == 0)
return;
NetProc*cur = last_;
do {
cur = cur->next_;
cur->nex_output(out);
} while (cur != last_);
}
void NetCase::nex_output(NexusSet&out)
{
for (unsigned idx = 0 ; idx < nitems_ ; idx += 1) {
assert(items_[idx].statement);
items_[idx].statement->nex_output(out);
}
}
void NetCondit::nex_output(NexusSet&out)
{
if (if_ != 0)
if_->nex_output(out);
if (else_ != 0)
else_->nex_output(out);
}
void NetEvWait::nex_output(NexusSet&out)
{
assert(statement_);
statement_->nex_output(out);
}
/*
* $Log: net_nex_output.cc,v $
* Revision 1.6 2002/09/17 04:39:20 steve
* Account for part select in l-value.
*
* Revision 1.5 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2002/07/29 00:00:28 steve
* Asynchronous synthesis of sequential blocks.
*
* Revision 1.3 2002/07/07 22:32:15 steve
* Asynchronous synthesis of case statements.
*
* Revision 1.2 2002/07/01 00:54:21 steve
* synth_asych of if/else requires redirecting the target
* if sub-statements. Use NetNet objects to manage the
* situation.
*
* Revision 1.1 2002/06/30 02:21:32 steve
* Add structure for asynchronous logic synthesis.
*
*/