34 lines
605 B
Verilog
34 lines
605 B
Verilog
// This tests positional binding of an interface-typed module port.
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//
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// This file is placed into the Public Domain, for any use, without
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// warranty.
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module test;
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bus_if bus();
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assign bus.value = 1'b1;
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bus_user dut(bus);
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initial begin
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#1;
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if (bus.sample !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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module bus_user(
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bus_if.consumer bus
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);
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assign bus.sample = bus.value;
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endmodule
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interface bus_if ();
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logic value;
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logic sample;
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modport consumer(input value, output sample);
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endinterface
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