31 lines
543 B
Verilog
31 lines
543 B
Verilog
// Check that continuous array assignment to single element unpacked arrays is
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// supported.
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module test;
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reg failed;
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wire [31:0] a[0:0];
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reg [31:0] b[0:0];
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assign a = b;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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b[0] = 32'd42;
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#1;
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`check(a[0], 32'd42);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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