28 lines
509 B
Verilog
28 lines
509 B
Verilog
// Check that procedural assignment of unpacked array assignment patterns to
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// single element arrays is supported.
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module test;
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reg failed;
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integer a[0:0];
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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a = '{42};
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`check(a[0], 42);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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