136 lines
4.7 KiB
C++
136 lines
4.7 KiB
C++
#ifndef __target_H
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#define __target_H
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/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: target.h,v 1.3 1998/11/09 18:55:35 steve Exp $"
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#endif
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# include "netlist.h"
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class ostream;
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/*
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* This header file describes the types and constants used to describe
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* the possible target output types of the compiler. The backends
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* provide one of these in order to tell the previous steps what the
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* backend is able to do.
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*/
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/*
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* The backend driver is hooked into the compiler, and given a name,
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* by creating an instance of the target structure. The structure has
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* the name that the compiler will use to locate the driver, and a
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* pointer to a target_t object that is the actual driver.
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*/
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struct target {
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string name;
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struct target_t* meth;
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};
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/*
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* The emit process uses a target_t driver to send the completed
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* design to a file. It is up to the driver object to follow along in
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* the iteration through the design, generating output as it can.
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*/
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struct target_t {
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virtual ~target_t();
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/* Start the design. */
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virtual void start_design(ostream&os, const Design*);
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/* Output a signal (called for each signal) */
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virtual void signal(ostream&os, const NetNet*);
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/* Output a gate (called for each gate) */
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virtual void logic(ostream&os, const NetLogic*);
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virtual void bufz(ostream&os, const NetBUFZ*);
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virtual void net_assign(ostream&os, const NetAssign*);
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virtual void net_const(ostream&os, const NetConst*);
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virtual void net_pevent(ostream&os, const NetPEvent*);
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/* Output a process (called for each process) */
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virtual void start_process(ostream&os, const NetProcTop*);
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/* Various kinds of process nodes are dispatched through these. */
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virtual void proc_assign(ostream&os, const NetAssign*);
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virtual void proc_block(ostream&os, const NetBlock*);
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virtual void proc_condit(ostream&os, const NetCondit*);
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virtual void proc_task(ostream&os, const NetTask*);
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virtual void proc_while(ostream&os, const NetWhile*);
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virtual void proc_event(ostream&os, const NetPEvent*);
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virtual void proc_delay(ostream&os, const NetPDelay*);
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/* (called for each process) */
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virtual void end_process(ostream&os, const NetProcTop*);
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/* Done with the design. */
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virtual void end_design(ostream&os, const Design*);
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};
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/* This class is used by the NetExpr class to help with the scanning
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of expressions. */
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struct expr_scan_t {
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virtual ~expr_scan_t();
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virtual void expr_const(const NetEConst*);
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virtual void expr_ident(const NetEIdent*);
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virtual void expr_signal(const NetESignal*);
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virtual void expr_unary(const NetEUnary*);
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virtual void expr_binary(const NetEBinary*);
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};
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/* The emit functions take a design and emit it to the output stream
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using the specified target. If the target is given by name, it is
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located in the target_table and used. */
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extern void emit(ostream&o, const Design*des, const char*type);
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/* This function takes a fully qualified verilog name (which may have,
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for example, dots in it) and produces a mangled version that can be
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used by most any language. */
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extern string mangle(const string&str);
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/* This is the table of supported output targets. It is a null
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terminated array of pointers to targets. */
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extern const struct target *target_table[];
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/*
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* $Log: target.h,v $
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* Revision 1.3 1998/11/09 18:55:35 steve
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* Add procedural while loops,
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* Parse procedural for loops,
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* Add procedural wait statements,
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* Add constant nodes,
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* Add XNOR logic gate,
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* Make vvm output look a bit prettier.
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*
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* Revision 1.2 1998/11/07 17:05:06 steve
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* Handle procedural conditional, and some
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* of the conditional expressions.
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*
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* Elaborate signals and identifiers differently,
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* allowing the netlist to hold signal information.
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*
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* Revision 1.1 1998/11/03 23:29:06 steve
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* Introduce verilog to CVS.
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*
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*/
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#endif
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