iverilog/searchindex.js

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"locat": 49, "includ": 49, "direct": 49, "report": 50, "good": 50, "make": 51, "advanc": 51, "input": 51, "optim": 52, "vhdlpp": 53, "It": 54, "work": [54, 58], "return": 54, "pli": 54, "refer": 54, "mode": 55, "enter": 55, "brows": 55, "design": 55, "leav": 55, "vcd": 56, "fst": 56, "lxt": 56, "sdf": 56, "environ": 56, "view": 58, "waveform": 58}, "envversion": {"sphinx.domains.c": 3, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 9, "sphinx.domains.index": 1, "sphinx.domains.javascript": 3, "sphinx.domains.math": 2, "sphinx.domains.python": 4, "sphinx.domains.rst": 2, "sphinx.domains.std": 2, "sphinx": 60}, "alltitles": {"Getting Started as a Contributor": [[0, "getting-started-as-a-contributor"]], "Getting Icarus Verilog": [[0, "getting-icarus-verilog"]], "Icarus Specific Configuration Options": [[0, "icarus-specific-configuration-options"], [48, "icarus-specific-configuration-options"]], "Compiling on Linux": [[0, "compiling-on-linux"]], "Regression Tests": [[0, "regression-tests"]], "Forks, Branches and Pull Requests": [[0, "forks-branches-and-pull-requests"]], "Glossary": [[1, "glossary"]], "Cadence PLI1 Modules": [[2, "cadence-pli1-modules"]], "Developer Guide": [[3, "developer-guide"]], "Compiler Components": [[3, "compiler-components"]], "Runtime Components": [[3, "runtime-components"]], "The Core Compiler": [[3, "the-core-compiler"]], "Further Reading": [[3, "further-reading"]], "Icarus Verilog Attributes": [[4, "icarus-verilog-attributes"]], "Attribute Naming Conventions": [[4, "attribute-naming-conventions"]], "Attributes To Control Synthesis": [[4, "attributes-to-control-synthesis"]], "Misc": [[4, "misc"]], "IVL - The Core Compiler": [[5, "ivl-the-core-compiler"]], "Loadable Target API (ivl_target)": [[6, "loadable-target-api-ivl-target"]], "The Target Module API": [[6, "the-target-module-api"]], "Compiling Target Modules": [[6, "compiling-target-modules"], [9, "compiling-target-modules"]], "Creating the Target Config File": [[6, "creating-the-target-config-file"]], "Installing the Target Module": [[6, "installing-the-target-module"]], "LPM Devices": [[6, "lpm-devices"]], "What Is LPM": [[7, "what-is-lpm"]], "Internal Uses Of LPM": [[7, "internal-uses-of-lpm"]], "Netlist Format": [[8, "netlist-format"]], "Structural Items: NetNode and NetNet": [[8, "structural-items-netnode-and-netnet"]], "Structural Links": [[8, "structural-links"]], "Behavioral Items: NetProcTop, NetProc and derived classes": [[8, "behavioral-items-netproctop-netproc-and-derived-classes"]], "Interaction Of Behavioral And Structural: NetAssign_": [[8, "interaction-of-behavioral-and-structural-netassign"]], "Memories": [[8, "memories"]], "Expressions": [[8, "expressions"]], "Expression Bit Width": [[8, "expression-bit-width"]], "Interaction Of Expressions And Structure: NetESignal": [[8, "interaction-of-expressions-and-structure-netesignal"]], "Hierarchy In Netlists": [[8, "hierarchy-in-netlists"]], "Scope Representation In Netlists": [[8, "scope-representation-in-netlists"]], "Tasks In Netlists": [[8, "tasks-in-netlists"]], "Time Scale In Netlists": [[8, "time-scale-in-netlists"]], "Loadable Targets": [[9, "loadable-targets"]], "Loading Target Modules": [[9, "loading-target-modules"]], "Loadable Target Module Api": [[9, "loadable-target-module-api"]], "About Specific Expression Types": [[9, "about-specific-expression-types"]], "IEEE1364 Notes": [[10, "ieee1364-notes"]], "Standardization Issues": [[10, "standardization-issues"]], "Miscellaneous": [[11, "miscellaneous"]], "Swift Model Support (Preliminary)": [[12, "swift-model-support-preliminary"]], "Xilinx Hint": [[13, "xilinx-hint"]], "Verilog:": [[13, "verilog"]], "Running ivl:": [[13, "running-ivl"]], "Generating .pcf files:": [[13, "generating-pcf-files"]], "Downloading:": [[13, "downloading"]], "The VVP Target": [[14, "the-vvp-target"]], "Symbol Name Conventions": [[14, "symbol-name-conventions"]], "General Functor Web Structure": [[14, "general-functor-web-structure"]], "VPI in Icarus Verilog": [[15, "vpi-in-icarus-verilog"]], "Verilog-A math library": [[16, "verilog-a-math-library"]], "License.": [[16, "license"]], "Standard Verilog-A Mathematical Functions.": [[16, "standard-verilog-a-mathematical-functions"]], "Standard Verilog-A Mathematical Constants.": [[16, "standard-verilog-a-mathematical-constants"]], "Using the Library.": [[16, "using-the-library"]], "Thanks": [[16, "thanks"]], "VPI Modules in Icarus Verilog": [[17, "vpi-modules-in-icarus-verilog"]], "Compiling A VPI Module": [[17, "compiling-a-vpi-module"]], "Tracing VPI Use": [[17, "tracing-vpi-use"]], "Debug Aids For VVP": [[18, "debug-aids-for-vvp"]], "VVP - Verilog Virtual Processor": [[19, "vvp-verilog-virtual-processor"]], "Executable Instruction Opcodes": [[20, "executable-instruction-opcodes"]], "Flags": [[20, "flags"], [35, "flags"], [39, "flags"]], "VPI Within VVP": [[21, "vpi-within-vvp"]], "Loading VPI Modules": [[21, "loading-vpi-modules"]], "System Task Calls": [[21, "system-task-calls"]], "System Function Calls": [[21, "system-function-calls"]], "System Task/Function Arguments": [[21, "system-task-function-arguments"]], "Scopes": [[21, "scopes"]], "Variables": [[21, "variables"]], "Thread Details": [[22, "thread-details"]], "VVP Simulation Engine": [[23, "vvp-simulation-engine"]], "General Format": [[23, "general-format"]], "Header Syntax": [[23, "header-syntax"]], "Labels and Symbols": [[23, "labels-and-symbols"]], "Numbers": [[23, "numbers"]], "Scope Statements": [[23, "scope-statements"]], "Parameter Statements": [[23, "parameter-statements"]], "Functor Statements": [[23, "functor-statements"]], "DFF and Latch Statements": [[23, "dff-and-latch-statements"]], "UDP Statements": [[23, "udp-statements"]], "Variable Statements": [[23, "variable-statements"]], "Net Statements": [[23, "net-statements"]], "Cast Statements": [[23, "cast-statements"]], "Delay Statements": [[23, "delay-statements"]], "Module Path Delay Statements": [[23, "module-path-delay-statements"]], "Array Index Statements": [[23, "array-index-statements"]], "Event Statements": [[23, "event-statements"]], "Resolver Statements": [[23, "resolver-statements"]], "Part Select Statements": [[23, "part-select-statements"]], "Part Concatenation Statements": [[23, "part-concatenation-statements"]], "Repeat Vector Statements": [[23, "repeat-vector-statements"]], "Substitution Statements": [[23, "substitution-statements"]], "Reduction Logic": [[23, "reduction-logic"]], "Expansion Logic": [[23, "expansion-logic"]], "Force Statements (old method - remove me)": [[23, "force-statements-old-method-remove-me"]], "Force Statements (new method - implement me)": [[23, "force-statements-new-method-implement-me"]], "Structural Arithmetic Statements": [[23, "structural-arithmetic-statements"]], "Structural Compare Statements": [[23, "structural-compare-statements"]], "Structural Shifter Statements": [[23, "structural-shifter-statements"]], "Structural Function Calls": [[23, "structural-function-calls"]], "Thread Statements": [[23, "thread-statements"]], "Vpi Task/Function Calls": [[23, "vpi-task-function-calls"]], "Truth Tables": [[23, "truth-tables"]], "Executable Instructions": [[23, "executable-instructions"]], "The Relationship Between Functors, Threads And Events": [[23, "the-relationship-between-functors-threads-and-events"]], "VVP Compilation And Execution": [[23, "vvp-compilation-and-execution"]], "How To Get From There To Here": [[23, "how-to-get-from-there-to-here"]], "Automatically Allocated Scopes": [[23, "automatically-allocated-scopes"]], "Icarus Verilog Developer Support": [[24, "icarus-verilog-developer-support"]], "The Regression Test Suite": [[25, "the-regression-test-suite"]], "Test Descriptions": [[25, "test-descriptions"]], "source (required)": [[25, "source-required"]], "type (required)": [[25, "type-required"]], "gold (optional)": [[25, "gold-optional"]], "iverilog-args (optional)": [[25, "iverilog-args-optional"]], "vvp-args (optional)": [[25, "vvp-args-optional"]], "vvp-args-extended (optional)": [[25, "vvp-args-extended-optional"]], "strict, force-sv or vlog95 (optional)": [[25, "strict-force-sv-or-vlog95-optional"]], "Files With Version Information": [[26, "files-with-version-information"]], "Icarus Verilog": [[27, "icarus-verilog"]], "Contents:": [[27, null]], "Indices and tables": [[27, "indices-and-tables"]], "Icarus Verilog Release Notes": [[28, "icarus-verilog-release-notes"]], "\ud83c\udf89 Release V13.0": [[29, "release-v13-0"]], "\ud83d\udc1e Bug Fix Summary": [[29, "bug-fix-summary"]], "\ud83d\udd04 Major Changes in V13": [[29, "major-changes-in-v13"]], "\ud83e\udde0 Language & Elaboration Fixes": [[29, "language-elaboration-fixes"]], "\u2699\ufe0f Simulator (vvp) Improvements": [[29, "simulator-vvp-improvements"]], "\ud83d\udd0c VPI Updates": [[29, "vpi-updates"]], "\ud83d\udee0 Diagnostics & Toolchain": [[29, "diagnostics-toolchain"]], "\ud83d\udce6 Upgrade Notes": [[29, "upgrade-notes"]], "\ud83d\ude4f Acknowledgments": [[29, "acknowledgments"]], "The Icarus Verilog Targets": [[30, "the-icarus-verilog-targets"]], "The BLIF Code Generator (-tblif)": [[31, "the-blif-code-generator-tblif"]], "USAGE": [[31, "usage"]], "LIMITATIONS": [[31, "limitations"]], "The FPGA Code Generator (-tfpga)": [[32, "the-fpga-code-generator-tfpga"]], "INVOKING THE FPGA TARGET": [[32, "invoking-the-fpga-target"]], "XNF ROOT PORTS": [[32, "xnf-root-ports"]], "EDIF ROOT PORTS": [[32, "edif-root-ports"]], "PADS AND PIN ASSIGNMENT": [[32, "pads-and-pin-assignment"]], "SPECIAL DEVICES": [[32, "special-devices"]], "COMPILING WITH XILINX FOUNDATION": [[32, "compiling-with-xilinx-foundation"]], "The null Code Generator (-tnull)": [[33, "the-null-code-generator-tnull"]], "The PAL Code Generator (-tpal)": [[34, "the-pal-code-generator-tpal"]], "The PCB Code Generator (-tpcb)": [[35, "the-pcb-code-generator-tpcb"]], "Invocation": [[35, "invocation"], [39, "invocation"], [40, "invocation"]], "Attributes Summary": [[35, "attributes-summary"]], "Parameters Summary": [[35, "parameters-summary"]], "The sizer Code Analyzer (-tsizer)": [[36, "the-sizer-code-analyzer-tsizer"]], "The stub Code Generator (-tstub)": [[37, "the-stub-code-generator-tstub"]], "The Verilog Code Generator (-tverilog)": [[38, "the-verilog-code-generator-tverilog"]], "The VHDL Code Generator (-tvhdl)": [[39, "the-vhdl-code-generator-tvhdl"]], "Supported Constructs": [[39, "supported-constructs"]], "Limitations": [[39, "limitations"]], "Signal Values and Resolution": [[39, "signal-values-and-resolution"]], "Constructs Not Supported": [[39, "constructs-not-supported"]], "Other Limitations": [[39, "other-limitations"]], "The Verilog \u201895 Code Generator (-tvlog95)": [[40, "the-verilog-95-code-generator-tvlog95"]], "Generator Flags": [[40, "generator-flags"]], "Structures that cannot be converted to 1995 compatible Verilog": [[40, "structures-that-cannot-be-converted-to-1995-compatible-verilog"]], "Known Issues and Limitations": [[40, "known-issues-and-limitations"]], "The vvp Code Generator (-tvvp)": [[41, "the-vvp-code-generator-tvvp"]], "Opcodes": [[41, "opcodes"]], "Command File Format": [[42, "command-file-format"]], "Comments": [[42, "comments"]], "Plus-args": [[42, "plus-args"]], "File Names": [[42, "file-names"]], "Variable Substitution": [[42, "variable-substitution"]], "An Example": [[42, "an-example"]], "Summary": [[42, "summary"]], "iverilog Command Line Flags": [[43, "iverilog-command-line-flags"]], "General": [[43, "general"]], "Preprocessor Flags": [[43, "preprocessor-flags"]], "Elaboration Flags": [[43, "elaboration-flags"]], "Target Flags": [[43, "target-flags"]], "Getting Started With Icarus Verilog": [[44, "getting-started-with-icarus-verilog"]], "Icarus Verilog Extensions": [[45, "icarus-verilog-extensions"]], "System Functions": [[45, "system-functions"]], "$is_signed(<expr>)": [[45, "is-signed-expr"]], "$bits(<expr>), $sizeof(<expr>)": [[45, "bits-expr-sizeof-expr"]], "$simtime()": [[45, "simtime"]], "$mti_random(), $mti_dist_uniform": [[45, "mti-random-mti-dist-uniform"]], "System Tasks": [[45, "system-tasks"]], "$readmempath": [[45, "readmempath"]], "$finish_and_return(code)": [[45, "finish-and-return-code"]], "Extended Verilog Data Types": [[45, "extended-verilog-data-types"]], "Icarus Verilog Quirks": [[46, "icarus-verilog-quirks"]], "Unsized Numeric Constants are Not Limited to 32 Bits": [[46, "unsized-numeric-constants-are-not-limited-to-32-bits"]], "Unsized Expressions": [[46, "unsized-expressions"]], "Unsized Parameters": [[46, "unsized-parameters"]], "Unsized Expressions as Arguments to Concatenation": [[46, "unsized-expressions-as-arguments-to-concatenation"]], "Scope of Macro Defines Doesn\u2019t Extend into Libraries": [[46, "scope-of-macro-defines-doesn-t-extend-into-libraries"]], "Continuous Assign L-Values Can Implicit-Define Wires": [[46, "continuous-assign-l-values-can-implicit-define-wires"]], "Dumping Array Words ($dumpvars)": [[46, "dumping-array-words-dumpvars"]], "Referencing Declarations Within an Unnamed Generate Block": [[46, "referencing-declarations-within-an-unnamed-generate-block"]], "%g/%G Format Specifiers": [[46, "g-g-format-specifiers"]], "%t Time Format Specifier Can Specify Width": [[46, "t-time-format-specifier-can-specify-width"]], "%v Format Specifier Can Display Vectors": [[46, "v-format-specifier-can-display-vectors"]], "Assign/Deassign and Force/Release of Bit/Part Selects": [[46, "assign-deassign-and-force-release-of-bit-part-selects"]], "repeat Statement is Sign Aware": [[46, "repeat-statement-is-sign-aware"]], "Built-in System Functions May Be Evaluated at Compile Time": [[46, "built-in-system-functions-may-be-evaluated-at-compile-time"]], "vpiScope Iterator on vpiScope Objects": [[46, "vpiscope-iterator-on-vpiscope-objects"]], "Time 0 Race Resolution": [[46, "time-0-race-resolution"]], "Icarus Verilog Usage": [[47, "icarus-verilog-usage"]], "Installation Guide": [[48, "installation-guide"]], "Installation From Source": [[48, "installation-from-source"]], "Compiling on Linux/Unix": [[48, "compiling-on-linux-unix"]], "Compiling on Macintosh OS X": [[48, "compiling-on-macintosh-os-x"]], "Cross-Compiling for Windows": [[48, "cross-compiling-for-windows"]], "IVLPP - IVL Preprocessor": [[49, "ivlpp-ivl-preprocessor"]], "Flags File": [[49, "flags-file"]], "Locating Included Files": [[49, "locating-included-files"]], "Generated Line Directives": [[49, "generated-line-directives"]], "Reporting Issues": [[50, "reporting-issues"]], "Good Issue Reporting": [[50, "good-issue-reporting"]], "How To Create A Pull Request": [[50, "how-to-create-a-pull-request"]], "Simulation Using Icarus Verilog": [[51, "simulation-using-icarus-verilog"]], "Compilation and Elaboration": [[51, "compilation-and-elaboration"]], "Making and Using Libraries": [[51, "making-and-using-libraries"]], "The Macro Preprocessor": [[51, "the-macro-preprocessor"]], "Automatic Module Libraries": [[51, "automatic-module-libraries"]], "Advanced Command Files": [[51, "advanced-command-files"]], "Input Data at Runtime": [[51, "input-data-at-runtime"]], "Verilog Attributes": [[52, "verilog-attributes"]], "Optimizations": [[52, "optimizations"]], "Synthesis": [[52, "synthesis"]], "vhdlpp Command Line Flags": [[53, "vhdlpp-command-line-flags"]], "Library Format": [[53, "library-format"]], "Using VPI": [[54, "using-vpi"]], "How It Works": [[54, "how-it-works"]], "Compiling VPI Modules": [[54, "compiling-vpi-modules"]], "A Worked Example": [[54, "a-worked-example"]], "System Function Return Types": [[54, "system-function-return-types"]], "Cadence PLI Modules": [[54, "cadence-pli-modules"]], "Other References": [[54, "other-references"]], "VVP Interactive Mode": [[55, "vvp-interactive-mode"]], "Enter Interactive Mode": [[55, "enter-interactive-mode"]], "Browsing the Design": [[55, "browsing-the-design"]], "Leave Interactive Mode": [[55, "leave-interactive-mode"]], "VVP Command Line Flags": [[56, "vvp-command-line-flags"]], "Options/Flags": [[56, "options-flags"]], "Extended Arguments": [[56, "extended-arguments"]], "VCD/FST/LXT Arguments": [[56, "vcd-fst-lxt-arguments"]], "SDF Support": [[56, "sdf-support"]], "Environment Variables": [[56, "environment-variables"]], "VVP as a library": [[57, "vvp-as-a-library"]], "Viewing Waveforms": [[58, "viewing-waveforms"]], "Generating waveform dump files for viewing": [[58, "generating-waveform-dump-files-for-viewing"]], "A Working Example": [[58, "a-working-example"]]}, "indexentries": {}})