252 lines
6.7 KiB
C++
252 lines
6.7 KiB
C++
/*
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* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: xnfsyn.cc,v 1.3 1999/08/18 04:00:02 steve Exp $"
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#endif
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/*
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* The xnfsyn function searches the behavioral description for
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* patterns that are known to represent XNF library components. This
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* is especially interesting for the sequential components such as
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* flip flops and latches. As threads are transformed into components,
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* the design is rewritten.
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*
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* Currently, this transform recognizes the following patterns:
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*
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* always @(posedge CLK) Q = D // DFF:D,Q,C
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* always @(negedge CLK) Q = D // DFF:D,Q,~C
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*
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* always @(posedge CLK) if (CE) Q = D;
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* always @(negedge CLK) if (CE) Q = D;
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*
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* The r-value of the assignments must be identifiers (i.e. wires or
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* registers) and the CE must be single-bine identifiers. Enough
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* devices will be created to accommodate the width of Q and D, though
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* the CLK and CE will be shared by all the devices.
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*/
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# include "functor.h"
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# include "netlist.h"
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class xnfsyn_f : public functor_t {
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public:
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void process(class Design*, class NetProcTop*);
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private:
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void proc_always_(class Design*);
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void proc_casn_(class Design*);
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void proc_ccon_(class Design*);
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// The matcher does something like a recursive descent search
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// for the templates. These variables are filled in as the
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// searcher finds them.
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class NetProcTop*top_;
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class NetPEvent *pclk_;
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class NetNEvent *nclk_;
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class NetCondit *con_;
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class NetAssign *asn_;
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};
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/*
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* Look at a process, and divide the problem into always and initial
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* threads.
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*/
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void xnfsyn_f::process(class Design*des, class NetProcTop*top)
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{
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switch (top->type()) {
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case NetProcTop::KALWAYS:
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top_ = top;
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proc_always_(des);
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break;
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}
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}
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/*
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* An "always ..." statement has been found.
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*/
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void xnfsyn_f::proc_always_(class Design*des)
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{
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// The statement must be a NetPEvent, ...
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pclk_ = dynamic_cast<class NetPEvent*>(top_->statement());
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if (pclk_ == 0)
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return;
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// ... there must be a single event source, ...
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svector<class NetNEvent*>*neb = pclk_->back_list();
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if (neb == 0)
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return;
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if (neb->count() != 1) {
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delete neb;
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return;
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}
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nclk_ = (*neb)[0];
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delete neb;
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// ... the event must be an edge, ...
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switch (nclk_->type()) {
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case NetNEvent::POSEDGE:
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case NetNEvent::NEGEDGE:
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break;
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default:
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return;
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}
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// Is this a clocked assignment?
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asn_ = dynamic_cast<NetAssign*>(pclk_->statement());
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if (asn_) {
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proc_casn_(des);
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return;
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}
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con_ = dynamic_cast<NetCondit*>(pclk_->statement());
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if (con_) {
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proc_ccon_(des);
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return;
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}
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}
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/*
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* The process so far has been matched as:
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*
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* always @(posedge nclk_) asn_ = <r>;
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* always @(negedge nclk_) asn_ = <r>;
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*/
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void xnfsyn_f::proc_casn_(class Design*des)
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{
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// ... and the rval must be a simple signal.
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NetESignal*sig = dynamic_cast<NetESignal*>(asn_->rval());
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if (sig == 0) {
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cerr << "Noted complex rval in DFF, name " << asn_->name() <<
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", not yet implemented" << endl;
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return ;
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}
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// The signal and the assignment must be the same width...
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assert(asn_->pin_count() == sig->pin_count());
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// Generate enough DFF objects to handle the entire width.
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for (unsigned idx = 0 ; idx < asn_->pin_count() ; idx += 1) {
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// XXXX FIXME: Objects need unique names!
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NetUDP*dff = new NetUDP(asn_->name(), 3, true);
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connect(dff->pin(0), asn_->pin(idx));
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connect(dff->pin(1), sig->pin(idx));
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connect(dff->pin(2), nclk_->pin(0));
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switch (nclk_->type()) {
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case NetNEvent::POSEDGE:
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dff->attribute("XNF-LCA", "DFF:Q,D,C");
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break;
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case NetNEvent::NEGEDGE:
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dff->attribute("XNF-LCA", "DFF:Q,D,~C");
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break;
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}
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des->add_node(dff);
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}
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// This process is matched and replaced with a DFF. Get
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// rid of the now useless NetProcTop.
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des->delete_process(top_);
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}
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/*
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* The process so far has been matched as:
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*
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* always @(posedge nclk_) if ...;
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* always @(negedge nclk_) if ...;
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*/
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void xnfsyn_f::proc_ccon_(class Design*des)
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{
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if (con_->else_clause())
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return;
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asn_ = dynamic_cast<NetAssign*>(con_->if_clause());
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if (asn_ == 0)
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return;
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NetESignal*sig = dynamic_cast<NetESignal*>(asn_->rval());
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if (sig == 0)
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return;
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// The signal and the assignment must be the same width...
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assert(asn_->pin_count() == sig->pin_count());
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NetESignal*ce = dynamic_cast<NetESignal*>(con_->expr());
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if (ce == 0)
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return;
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if (ce->pin_count() != 1)
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return;
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// Generate enough DFF objects to handle the entire width.
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for (unsigned idx = 0 ; idx < asn_->pin_count() ; idx += 1) {
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// XXXX FIXME: Objects need unique names!
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NetUDP*dff = new NetUDP(asn_->name(), 4, true);
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connect(dff->pin(0), asn_->pin(idx));
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connect(dff->pin(1), sig->pin(idx));
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connect(dff->pin(2), nclk_->pin(0));
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connect(dff->pin(3), ce->pin(0));
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switch (nclk_->type()) {
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case NetNEvent::POSEDGE:
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dff->attribute("XNF-LCA", "DFF:Q,D,C,CE");
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break;
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case NetNEvent::NEGEDGE:
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dff->attribute("XNF-LCA", "DFF:Q,D,~C,CE");
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break;
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}
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des->add_node(dff);
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}
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// This process is matched and replaced with a DFF. Get
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// rid of the now useless NetProcTop.
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des->delete_process(top_);
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}
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void xnfsyn(Design*des)
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{
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xnfsyn_f xnfsyn_obj;
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des->functor(&xnfsyn_obj);
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}
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/*
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* $Log: xnfsyn.cc,v $
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* Revision 1.3 1999/08/18 04:00:02 steve
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* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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*
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* Revision 1.2 1999/07/18 21:17:51 steve
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* Add support for CE input to XNF DFF, and do
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* complete cleanup of replaced design nodes.
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*
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* Revision 1.1 1999/07/18 05:52:47 steve
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* xnfsyn generates DFF objects for XNF output, and
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* properly rewrites the Design netlist in the process.
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*
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*/
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