134 lines
3.7 KiB
C++
134 lines
3.7 KiB
C++
#ifndef __PWire_H
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#define __PWire_H
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/*
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* Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: PWire.h,v 1.10 2001/01/16 02:44:18 steve Exp $"
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#endif
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# include "netlist.h"
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# include "LineInfo.h"
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# include <map>
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# include "svector.h"
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#ifdef HAVE_IOSFWD
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# include <iosfwd>
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#else
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class ostream;
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#endif
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class PExpr;
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class Design;
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/*
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* Wires include nets, registers and ports. A net or register becomes
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* a port by declaration, so ports are not seperate. The module
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* identifies a port by keeping it in its port list.
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*/
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class PWire : public LineInfo {
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public:
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PWire(const string&n, NetNet::Type t, NetNet::PortType pt);
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const string&name() const { return name_; }
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NetNet::Type get_wire_type() const;
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bool set_wire_type(NetNet::Type);
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NetNet::PortType get_port_type() const;
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bool set_port_type(NetNet::PortType);
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void set_signed(bool flag);
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bool get_signed() const;
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void set_range(PExpr*msb, PExpr*lsb);
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void set_memory_idx(PExpr*ldx, PExpr*rdx);
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map<string,string> attributes;
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// Write myself to the specified stream.
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void dump(ostream&out) const;
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void elaborate_sig(Design*, NetScope*scope) const;
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private:
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string name_;
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NetNet::Type type_;
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NetNet::PortType port_type_;
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bool signed_;
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// These members hold expressions for the bit width of the
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// wire. If they do not exist, the wire is 1 bit wide.
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svector<PExpr*>msb_;
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svector<PExpr*>lsb_;
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// If this wire is actually a memory, these indices will give
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// me the size and address range of the memory.
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PExpr*lidx_;
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PExpr*ridx_;
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private: // not implemented
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PWire(const PWire&);
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PWire& operator= (const PWire&);
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};
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/*
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* $Log: PWire.h,v $
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* Revision 1.10 2001/01/16 02:44:18 steve
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* Use the iosfwd header if available.
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*
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* Revision 1.9 2000/12/11 00:31:43 steve
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* Add support for signed reg variables,
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* simulate in t-vvm signed comparisons.
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*
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* Revision 1.8 2000/05/02 16:27:38 steve
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* Move signal elaboration to a seperate pass.
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*
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* Revision 1.7 2000/02/23 02:56:54 steve
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* Macintosh compilers do not support ident.
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*
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* Revision 1.6 1999/11/27 19:07:57 steve
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* Support the creation of scopes.
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*
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* Revision 1.5 1999/06/17 05:34:42 steve
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* Clean up interface of the PWire class,
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* Properly match wire ranges.
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*
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* Revision 1.4 1999/06/02 15:38:46 steve
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* Line information with nets.
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*
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* Revision 1.3 1999/04/19 01:59:36 steve
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* Add memories to the parse and elaboration phases.
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*
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* Revision 1.2 1998/11/23 00:20:22 steve
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* NetAssign handles lvalues as pin links
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* instead of a signal pointer,
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* Wire attributes added,
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* Ability to parse UDP descriptions added,
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* XNF generates EXT records for signals with
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* the PAD attribute.
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*
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* Revision 1.1 1998/11/03 23:28:55 steve
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* Introduce verilog to CVS.
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*
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*/
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#endif
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