40 lines
716 B
Verilog
40 lines
716 B
Verilog
// Check that string literals longer than the target byte array are truncated.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %02h, got %02h", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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byte desc [1:0] = "ABC";
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byte asc [0:1];
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byte unsized [2];
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assign asc = "ABC";
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initial begin
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#1;
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`check(desc[1], 8'h41);
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`check(desc[0], 8'h42);
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`check(asc[0], 8'h41);
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`check(asc[1], 8'h42);
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unsized = "ABCD";
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`check(unsized[0], 8'h41);
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`check(unsized[1], 8'h42);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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