62 lines
1.3 KiB
Verilog
62 lines
1.3 KiB
Verilog
// Check that string literals can be assigned to nested byte arrays using
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// assignment patterns.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %02h, got %02h", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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byte desc [0:1][3:0] = '{"AB\n", "CD\t"};
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byte asc [1:0][0:3];
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byte unsized [2][4];
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assign asc = '{"AB\n", "CD\t"};
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initial begin
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#1;
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`check(desc[0][3], 8'h41);
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`check(desc[0][2], 8'h42);
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`check(desc[0][1], 8'h0a);
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`check(desc[0][0], 8'h00);
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`check(desc[1][3], 8'h43);
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`check(desc[1][2], 8'h44);
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`check(desc[1][1], 8'h09);
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`check(desc[1][0], 8'h00);
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`check(asc[0][0], 8'h43);
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`check(asc[0][1], 8'h44);
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`check(asc[0][2], 8'h09);
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`check(asc[0][3], 8'h00);
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`check(asc[1][0], 8'h41);
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`check(asc[1][1], 8'h42);
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`check(asc[1][2], 8'h0a);
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`check(asc[1][3], 8'h00);
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unsized = '{"AB\n", "CD\t"};
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`check(unsized[0][0], 8'h41);
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`check(unsized[0][1], 8'h42);
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`check(unsized[0][2], 8'h0a);
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`check(unsized[0][3], 8'h00);
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`check(unsized[1][0], 8'h43);
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`check(unsized[1][1], 8'h44);
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`check(unsized[1][2], 8'h09);
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`check(unsized[1][3], 8'h00);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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