63 lines
1.2 KiB
Verilog
63 lines
1.2 KiB
Verilog
// Check that drive strength can be specified between the net type and the data
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// type in a net declaration and that vector gate arrays resolve strengths
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// correctly.
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module test;
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reg [7:0] pullval;
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wire (weak0, weak1) [7:0] value = pullval;
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reg [7:0] en0;
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reg [7:0] en1;
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reg failed = 1'b0;
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`define check(expr, val) \
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if ((expr) !== (val)) begin \
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$display("FAILED(%0d): `%s`, expected %0h, got %0h", `__LINE__, \
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`"expr`", (val), (expr)); \
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failed = 1'b1; \
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end
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buf (highz0, strong1) drive0 [7:0] (value, en0);
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not (strong0, highz1) drive1 [7:0] (value, en1);
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initial begin
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en0 = 8'h00;
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en1 = 8'h00;
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pullval = 8'hff;
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#1 `check(value, 8'hff)
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pullval = 8'h00;
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#1 `check(value, 8'h00)
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en0 = 8'haa;
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pullval = 8'hff;
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#1 `check(value, 8'hff)
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pullval = 8'h00;
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#1 `check(value, 8'haa)
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en0 = 8'h00;
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en1 = 8'hff;
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pullval = 8'hff;
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#1 `check(value, 8'h00)
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pullval = 8'h00;
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#1 `check(value, 8'h00)
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en0 = 8'hff;
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en1 = 8'hff;
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pullval = 8'hff;
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#1 `check(value, 8'hxx)
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pullval = 8'h00;
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#1 `check(value, 8'hxx)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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