289 lines
7.2 KiB
C
289 lines
7.2 KiB
C
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: verilog.c,v 1.4 2000/09/26 00:30:07 steve Exp $"
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#endif
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/*
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* This is a sample target module. All this does is write to the
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* output file some information about each object handle when each of
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* the various object functions is called. This can be used to
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* understand the behavior of the core as it uses a target module.
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*/
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# include <ivl_target.h>
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# include <stdio.h>
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static FILE*out;
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int target_start_design(ivl_design_t des)
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{
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const char*path = ivl_get_flag(des, "-o");
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if (path == 0) {
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return -1;
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}
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out = fopen(path, "w");
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if (out == 0) {
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perror(path);
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return -2;
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}
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fprintf(out, "module %s;\n", ivl_get_root_name(des));
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return 0;
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}
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void target_end_design(ivl_design_t des)
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{
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fprintf(out, "endmodule\n");
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fclose(out);
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}
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int target_net_bufz(const char*name, ivl_net_bufz_t net)
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{
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fprintf(out, "STUB: %s: BUFZ\n", name);
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return 0;
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}
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int target_net_const(const char*name, ivl_net_const_t net)
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{
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fprintf(out, "STUB: %s: constant\n", name);
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return 0;
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}
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int target_net_event(const char*name, ivl_net_event_t net)
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{
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fprintf(out, "STUB: %s: event\n", name);
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return 0;
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}
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int target_net_logic(const char*name, ivl_net_logic_t net)
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{
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unsigned npins, idx;
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switch (ivl_get_logic_type(net)) {
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case IVL_LO_AND:
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fprintf(out, " and %s (%s", name,
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ivl_get_nexus_name(ivl_get_logic_pin(net, 0)));
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break;
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case IVL_LO_OR:
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fprintf(out, " or %s (%s", name,
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ivl_get_nexus_name(ivl_get_logic_pin(net, 0)));
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break;
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default:
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fprintf(out, "STUB: %s: unsupported gate\n", name);
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return -1;
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}
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npins = ivl_get_logic_pins(net);
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for (idx = 1 ; idx < npins ; idx += 1)
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fprintf(out, ", %s",
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ivl_get_nexus_name(ivl_get_logic_pin(net,idx)));
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fprintf(out, ");\n");
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return 0;
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}
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int target_net_probe(const char*name, ivl_net_probe_t net)
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{
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fprintf(out, "STUB: %s: probe\n", name);
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return 0;
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}
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int target_net_signal(const char*name, ivl_signal_t net)
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{
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fprintf(out, "STUB: %s: signal [%u]\n", name, ivl_signal_pins(net));
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return 0;
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}
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static void show_expression(ivl_expr_t net)
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{
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if (net == 0)
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return;
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switch (ivl_expr_type(net)) {
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case IVL_EX_NUMBER: {
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int sigflag = ivl_expr_signed(net);
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unsigned idx, width = ivl_expr_width(net);
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const char*bits = ivl_expr_bits(net);
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fprintf(out, "%u'%sb", width, sigflag? "s" : "");
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for (idx = width ; idx > 0 ; idx -= 1)
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fprintf(out, "%c", bits[idx-1]);
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break;
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}
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case IVL_EX_STRING:
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fprintf(out, "\"%s\"", ivl_expr_string(net));
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break;
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case IVL_EX_SIGNAL:
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fprintf(out, "%s", ivl_expr_name(net));
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break;
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default:
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fprintf(out, "...");
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}
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}
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static void show_statement(ivl_statement_t net, unsigned ind)
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{
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const ivl_statement_type_t code = ivl_statement_type(net);
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switch (code) {
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case IVL_ST_ASSIGN:
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fprintf(out, "%*s? = ?;\n", ind, "");
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break;
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case IVL_ST_BLOCK: {
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unsigned cnt = ivl_stmt_block_count(net);
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unsigned idx;
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fprintf(out, "%*sbegin\n", ind, "");
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for (idx = 0 ; idx < cnt ; idx += 1) {
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ivl_statement_t cur = ivl_stmt_block_stmt(net, idx);
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show_statement(cur, ind+4);
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}
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fprintf(out, "%*send\n", ind, "");
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break;
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}
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case IVL_ST_CONDIT: {
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ivl_statement_t t = ivl_stmt_cond_true(net);
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ivl_statement_t f = ivl_stmt_cond_false(net);
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fprintf(out, "%*sif (...)\n", ind, "");
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if (t)
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show_statement(t, ind+4);
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else
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fprintf(out, "%*s;\n", ind+4, "");
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if (f) {
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fprintf(out, "%*selse\n", ind, "");
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show_statement(f, ind+4);
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}
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break;
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}
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case IVL_ST_DELAY:
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fprintf(out, "%*s#%lu\n", ind, "", ivl_stmt_delay_val(net));
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show_statement(ivl_stmt_sub_stmt(net), ind+2);
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break;
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case IVL_ST_NOOP:
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fprintf(out, "%*s/* noop */;\n", ind, "");
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break;
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case IVL_ST_STASK:
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if (ivl_stmt_parm_count(net) == 0) {
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fprintf(out, "%*s%s;\n", ind, "", ivl_stmt_name(net));
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} else {
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unsigned idx;
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fprintf(out, "%*s%s(", ind, "", ivl_stmt_name(net));
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show_expression(ivl_stmt_parm(net, 0));
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for (idx = 1 ; idx < ivl_stmt_parm_count(net) ; idx += 1) {
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fprintf(out, ", ");
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show_expression(ivl_stmt_parm(net, idx));
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}
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fprintf(out, ");\n");
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}
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break;
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case IVL_ST_WAIT:
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fprintf(out, "%*s@(...)\n", ind, "");
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show_statement(ivl_stmt_sub_stmt(net), ind+2);
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break;
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case IVL_ST_WHILE:
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fprintf(out, "%*swhile (<?>)\n", ind, "");
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show_statement(ivl_stmt_sub_stmt(net), ind+2);
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break;
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default:
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fprintf(out, "%*sunknown statement type (%u)\n", ind, "", code);
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}
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}
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int target_process(ivl_process_t net)
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{
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switch (ivl_get_process_type(net)) {
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case IVL_PR_INITIAL:
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fprintf(out, " initial\n");
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break;
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case IVL_PR_ALWAYS:
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fprintf(out, " always\n");
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break;
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}
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show_statement(ivl_get_process_stmt(net), 8);
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return 0;
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}
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/*
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* $Log: verilog.c,v $
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* Revision 1.4 2000/09/26 00:30:07 steve
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* Add EX_NUMBER and ST_TRIGGER to dll-api.
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*
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* Revision 1.3 2000/09/24 15:46:00 steve
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* API access to signal type and port type.
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*
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* Revision 1.2 2000/09/24 02:21:54 steve
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* Add support for signal expressions.
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*
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* Revision 1.1 2000/09/23 05:15:07 steve
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* Add enough tgt-verilog code to support hello world.
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*
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* Revision 1.9 2000/09/22 03:58:30 steve
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* Access to the name of a system task call.
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*
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* Revision 1.8 2000/09/19 04:15:27 steve
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* Introduce the means to get statement types.
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*
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* Revision 1.7 2000/09/18 01:24:32 steve
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* Get the structure for ivl_statement_t worked out.
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*
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* Revision 1.6 2000/08/27 15:51:51 steve
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* t-dll iterates signals, and passes them to the
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* target module.
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*
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* Some of NetObj should return char*, not string.
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*
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* Revision 1.5 2000/08/26 00:54:03 steve
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* Get at gate information for ivl_target interface.
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*
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* Revision 1.4 2000/08/20 04:13:57 steve
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* Add ivl_target support for logic gates, and
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* make the interface more accessible.
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*
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* Revision 1.3 2000/08/19 18:12:42 steve
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* Add target calls for scope, events and logic.
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*
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* Revision 1.2 2000/08/14 04:39:57 steve
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* add th t-dll functions for net_const, net_bufz and processes.
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*
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* Revision 1.1 2000/08/12 16:34:37 steve
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* Start stub for loadable targets.
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*
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*/
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