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180 lines
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<title>The vvp Code Generator (-tvvp) — Icarus Verilog documentation</title>
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<section id="the-vvp-code-generator-tvvp">
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<h1>The vvp Code Generator (-tvvp)<a class="headerlink" href="#the-vvp-code-generator-tvvp" title="Link to this heading">¶</a></h1>
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<p>The vvp target generates code for the “vvp” run time. This is the most
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commonly used target for Icarus Verilog, as it is the main simulation engine.</p>
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<p>Example command:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -o top.vvp -s top hello_world.v
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</pre></div>
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</div>
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<p>Equivalent command:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -o top.vvp -tvvp -s top hello_world.v
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</pre></div>
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</div>
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<p>With this example code in <cite>hello_world.v</cite>:</p>
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<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">top</span><span class="p">;</span>
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<span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"Hello World!"</span><span class="p">);</span>
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<span class="k">endmodule</span>
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</pre></div>
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</div>
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<p>The resulting <cite>top.vvp</cite> will contain something similar to:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>#! /usr/local/bin/vvp
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:ivl_version "13.0 (devel)" "(s20221226-119-g8cb2e1a05-dirty)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/local/lib/ivl/system.vpi";
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:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
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:vpi_module "/usr/local/lib/ivl/va_math.vpi";
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S_0x563c3c5d1540 .scope module, "top" "top" 2 1;
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.timescale 0 0;
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.scope S_0x563c3c5d1540;
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T_0 ;
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%vpi_call 2 2 "$display", "Hello World!" {0 0 0};
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%end;
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.thread T_0;
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# The file index is used to find the file name in the following table.
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:file_names 3;
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"N/A";
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"<interactive>";
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"hello_world.v";
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</pre></div>
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</div>
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<p>The first line contains the shebang. If this file is executed, the shebang tells the shell to use vvp for the execution of this file.</p>
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<p>To run the simulation, execute:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% ./top.vvp
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</pre></div>
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</div>
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<p>Or you can call vvp directly:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% vvp top.vvp
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</pre></div>
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</div>
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<p>Next are some directives. The first one, <cite>:ivl_version</cite> specifies which version of iverilog this file was created with. Next is the delay selection with “min:typical:max” values and the time precision, which we did not set specifically, so the default value is used. The next lines tell vvp which VPI modules to load and in which order. The next lines tell vvp which VPI modules to load and in what order. Next, a new scope is created with the <cite>.scope</cite> directive and the timescale is set with <cite>.timescale</cite>. A thread <cite>T_0</cite> is created that contains two instructions: <cite>%vpi_call</cite> executes the VPI function <cite>$display</cite> with the specified arguments, and <cite>%end</cite> terminates the simulation.</p>
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<section id="opcodes">
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<h2>Opcodes<a class="headerlink" href="#opcodes" title="Link to this heading">¶</a></h2>
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<p>The various available opcodes can be seen in <a class="reference internal" href="../developer/guide/vvp/opcodes.html"><span class="doc">Opcodes</span></a></p>
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</section>
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</section>
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../releases/index.html">Icarus Verilog Release Notes</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-sizer.html">The sizer Code Analyzer (-tsizer)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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</ul>
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">The Icarus Verilog Targets</a><ul>
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<li>Previous: <a href="index.html" title="previous chapter">The Icarus Verilog Targets</a></li>
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<li>Next: <a href="tgt-stub.html" title="next chapter">The stub Code Generator (-tstub)</a></li>
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