150 lines
6.3 KiB
HTML
150 lines
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HTML
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<title>The stub Code Generator (-tstub) — Icarus Verilog documentation</title>
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<section id="the-stub-code-generator-tstub">
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<h1>The stub Code Generator (-tstub)<a class="headerlink" href="#the-stub-code-generator-tstub" title="Link to this heading">¶</a></h1>
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<p>The stub code generator is a debugging aid for the Icarus Verilog compiler
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itself. It outputs a text dump of the elaborated design as it is passed to
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code generators.</p>
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<p>Example command:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -o stub.txt -tstub -s top input.v
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</pre></div>
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</div>
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<p>With this example code:</p>
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<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">top</span><span class="p">;</span>
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<span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"Hello World!"</span><span class="p">);</span>
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<span class="k">endmodule</span>
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</pre></div>
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</div>
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<p>The resulting <cite>stub.txt</cite> will contain:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>root module = top
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scope: top (0 parameters, 0 signals, 0 logic) module top time units = 1e0
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time precision = 1e0
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end scope top
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# There are 0 constants detected
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initial
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Call $display(1 parameters); /* hello_world.v:2 */
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<string="Hello World!", width=96, type=bool>
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</pre></div>
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</div>
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</section>
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../releases/index.html">Icarus Verilog Release Notes</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-sizer.html">The sizer Code Analyzer (-tsizer)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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</ul>
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<div class="relations">
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">The Icarus Verilog Targets</a><ul>
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<li>Previous: <a href="tgt-vvp.html" title="previous chapter">The vvp Code Generator (-tvvp)</a></li>
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<li>Next: <a href="tgt-null.html" title="next chapter">The null Code Generator (-tnull)</a></li>
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