160 lines
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160 lines
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<title>The BLIF Code Generator (-tblif) — Icarus Verilog documentation</title>
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<section id="the-blif-code-generator-tblif">
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<h1>The BLIF Code Generator (-tblif)<a class="headerlink" href="#the-blif-code-generator-tblif" title="Link to this heading">¶</a></h1>
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<p>The BLIF code generator supports emitting the design to a blif format
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file as accepted by:</p>
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<blockquote>
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<div><p>ABC: A System for Sequential Synthesis and Verification
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<<a class="reference external" href="http://www.eecs.berkeley.edu/~alanmi/abc/">http://www.eecs.berkeley.edu/~alanmi/abc/</a>></p>
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</div></blockquote>
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<p>This package contains tools sometimes used by ASIC designers. This
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blif target emits .blif file that the ABC system can read int via
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the “read_blif” command.</p>
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<section id="usage">
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<h2>USAGE<a class="headerlink" href="#usage" title="Link to this heading">¶</a></h2>
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<p>This code generator is intended to process structural Verilog source
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code. To convert a design to blif, use this command:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -tblif -o<path>.blif <source files>...
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</pre></div>
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</div>
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<p>The source files can be Verilog, SystemVerilog, VHDL, whatever Icarus
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Verilog supports, so long as it elaborates down to the limited subset
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that the code generator supports. In other words, the files must be
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structural.</p>
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<p>The root module of the elaborated design becomes the model is
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generated. That module may instantiate sub-modules and so on down the
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design, completing the design. The output model is flattened, so it
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doesn’t invoke any subcircuits. Bit vectors are exploded out at the
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model ports and internally. This is necessary since blif in particular
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and ABC in general processes bits, not vectors.</p>
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</section>
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<section id="limitations">
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<h2>LIMITATIONS<a class="headerlink" href="#limitations" title="Link to this heading">¶</a></h2>
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<p>Currently, only explicit logic gates and continuous assignments are
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supported.</p>
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<p>The design must contain only one root module. The name of that root
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module becomes the name of the blif model in the “.model” record.</p>
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</section>
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</section>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../releases/index.html">Icarus Verilog Release Notes</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-sizer.html">The sizer Code Analyzer (-tsizer)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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<h3>Related Topics</h3>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">The Icarus Verilog Targets</a><ul>
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<li>Next: <a href="../developer/index.html" title="next chapter">Icarus Verilog Developer Support</a></li>
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