150 lines
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150 lines
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HTML
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<title>The VVP Target — Icarus Verilog documentation</title>
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<section id="the-vvp-target">
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<h1>The VVP Target<a class="headerlink" href="#the-vvp-target" title="Link to this heading">¶</a></h1>
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<section id="symbol-name-conventions">
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<h2>Symbol Name Conventions<a class="headerlink" href="#symbol-name-conventions" title="Link to this heading">¶</a></h2>
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<p>There are some naming conventions that the vvp target uses for
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generating symbol names.</p>
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<ul class="simple">
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<li><p>wires and regs</p></li>
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</ul>
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<p>Nets and variables are named V_<full-name> where <full-name> is the
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full hierarchical name of the signal.</p>
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<ul class="simple">
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<li><p>Logic devices</p></li>
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</ul>
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<p>Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
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this case the symbol is attached to a functor that is the output of
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the logic device.</p>
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</section>
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<section id="general-functor-web-structure">
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<h2>General Functor Web Structure<a class="headerlink" href="#general-functor-web-structure" title="Link to this heading">¶</a></h2>
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<p>The net of gates, signals and resolvers is formed from the input
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design. The basic structure is wrapped around the nexus, which is
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represented by the ivl_nexus_t.</p>
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<p>Each nexus represents a resolved value. The input of the nexus is fed
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by a single driver. If the nexus in the design has multiple drivers,
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the drivers are first fed into a resolver (or a tree of resolvers) to
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form a single output that is the nexus.</p>
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<p>The nexus, then, feeds its output to the inputs of other gates, or to
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the .net objects in the design.</p>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../../../releases/index.html">Icarus Verilog Release Notes</a></li>
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<li><a href="../index.html">Developer Guide</a><ul>
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<li>Previous: <a href="../vvp/debug.html" title="previous chapter">Debug Aids For VVP</a></li>
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<li>Next: <a href="../vpi/index.html" title="next chapter">VPI in Icarus Verilog</a></li>
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