iverilog/tgt-vhdl
Nick Gasson 3dadedf9b5 Fix VHDL bug where constant is assigned to input
This fixes a bug where the VHDL target would not
map ports in cases where the port was driven by
a constant.
2009-01-28 17:45:24 -08:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Move VHDL global state management to a single file 2009-01-17 09:19:58 -08:00
cast.cc VHDL fix concatenation of std_logics 2009-01-25 07:59:06 -08:00
display.cc Handle %m in VHDL $display code 2009-01-25 07:55:20 -08:00
expr.cc Fix various problems with VHDL `buffer' port generation 2009-01-25 07:49:54 -08:00
logic.cc Fix some more errors when reading from VHDL outputs 2009-01-25 07:50:03 -08:00
lpm.cc Fix some more errors when reading from VHDL outputs 2009-01-25 07:50:03 -08:00
process.cc Clean up VHDL debug messages 2009-01-17 09:19:58 -08:00
scope.cc Fix VHDL bug where constant is assigned to input 2009-01-28 17:45:24 -08:00
state.cc Various signal naming fixes for VHDL target 2009-01-28 17:44:14 -08:00
state.hh Various signal naming fixes for VHDL target 2009-01-28 17:44:14 -08:00
stmt.cc VHDL fix concatenation of std_logics 2009-01-25 07:59:06 -08:00
support.cc Move VHDL global state management to a single file 2009-01-17 09:19:58 -08:00
support.hh Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
vhdl-s.conf Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
vhdl.cc Move VHDL global state management to a single file 2009-01-17 09:19:58 -08:00
vhdl.conf Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Improve memory management in VHDL target 2009-01-18 16:42:10 -08:00
vhdl_element.hh Improve memory management in VHDL target 2009-01-18 16:42:10 -08:00
vhdl_helper.hh Improve memory management in VHDL target 2009-01-18 16:42:10 -08:00
vhdl_syntax.cc Fix VHDL bug where constant is assigned to input 2009-01-28 17:45:24 -08:00
vhdl_syntax.hh Fix VHDL bug where constant is assigned to input 2009-01-28 17:45:24 -08:00
vhdl_target.h Fix some more errors when reading from VHDL outputs 2009-01-25 07:50:03 -08:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00