27 lines
479 B
Verilog
27 lines
479 B
Verilog
// Regression: iterator index querying item.index in with() (LRM 7.12.4).
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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int arr[] = '{0, 1, 3, 3};
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int q[$];
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initial begin
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q = arr.find with (item == item.index);
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`CHK(q.size == 3);
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`CHK(q[0] == 0);
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`CHK(q[1] == 1);
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`CHK(q[2] == 3);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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