45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
// Accellera Standard V2.8.1 Open Verification Library (OVL).
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// Accellera Copyright (c) 2005-2014. All rights reserved.
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`include "std_ovl_defines.h"
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`module ovl_implication (clock, reset, enable, antecedent_expr, consequent_expr, fire);
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parameter severity_level = `OVL_SEVERITY_DEFAULT;
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parameter property_type = `OVL_PROPERTY_DEFAULT;
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parameter msg = `OVL_MSG_DEFAULT;
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parameter coverage_level = `OVL_COVER_DEFAULT;
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parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
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parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
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parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
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input clock, reset, enable;
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input antecedent_expr, consequent_expr;
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output [`OVL_FIRE_WIDTH-1:0] fire;
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// Parameters that should not be edited
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parameter assert_name = "OVL_IMPLICATION";
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`include "std_ovl_reset.h"
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`include "std_ovl_clock.h"
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`include "std_ovl_cover.h"
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`include "std_ovl_task.h"
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`include "std_ovl_init.h"
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`ifdef OVL_VERILOG
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`include "./vlog95/ovl_implication_logic.v"
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`endif
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`ifdef OVL_SVA
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`include "./sva05/ovl_implication_logic.sv"
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`endif
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`ifdef OVL_PSL
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`include "./psl05/assert_implication_psl_logic.v"
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`else
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assign fire = {fire_cover, fire_xcheck, fire_2state};
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`endmodule // ovl_implication
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`endif
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