62 lines
1.7 KiB
Plaintext
62 lines
1.7 KiB
Plaintext
:vpi_module "system";
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; Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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;
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; This source code is free software; you can redistribute it
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; and/or modify it in source code form under the terms of the GNU
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; General Public License as published by the Free Software
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; Foundation; either version 2 of the License, or (at your option)
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; any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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; This example shows how to wire up a simple adder. The code below is
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; like what might be generated from the Verilog:
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;
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; module main;
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; reg [3:0] A, B;
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; wire [3:0] Q = A + B;
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:
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: initial begin
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; A = 2;
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; B = 3;
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; #1 $display("%b %b = %b", A, B, Q);
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; end
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; endmodule
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;
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; Notice the use of the .arith/sum statment, including the specification
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; of the width (4 bits) and the order that the bits of the operands are
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; passed to the statement.
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S_main .scope "main";
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A .var "A", 3, 0;
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B .var "B", 3, 0;
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add .arith/sum 4, A[0], A[1], A[2], A[3], B[0], B[1], B[2], B[3];
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Q .net "Q", 3, 0, add[0], add[1], add[2], add[3];
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start %set A[0], 0;
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%set A[1], 1;
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%set A[2], 0;
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%set A[3], 0;
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%set B[0], 1;
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%set B[1], 1;
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%set B[2], 0;
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%set B[3], 0;
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%delay 1;
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%vpi_call "$display", "%b + %b == %b", A, B, Q;
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%end;
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.thread start;
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