85 lines
1.5 KiB
Verilog
85 lines
1.5 KiB
Verilog
// Check that assignment operators are supported on queue elements.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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integer x[$];
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integer i;
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initial begin
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x = '{0, 1};
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// Static index
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x[1] += 5;
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`check(x[1], 6);
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x[1] -= 2;
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`check(x[1], 4);
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x[1] *= 25;
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`check(x[1], 100);
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x[1] /= 5;
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`check(x[1], 20);
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x[1] %= 3;
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`check(x[1], 2);
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x[1] = 'haa;
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x[1] &= 'h33;
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`check(x[1], 'h22);
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x[1] |= 'h11;
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`check(x[1], 'h33);
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x[1] ^= 'h22;
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`check(x[1], 'h11);
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x[1] <<= 3;
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`check(x[1], 'h88);
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x[1] <<<= 1;
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`check(x[1], 'h110);
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x[1] >>= 2;
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`check(x[1], 'h44);
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x[1] >>>= 1;
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`check(x[1], 'h22);
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// Dynamic index
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x[1] = 1;
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i = 1;
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x[i] += 5;
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`check(x[i], 6);
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x[i] -= 2;
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`check(x[i], 4);
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x[i] *= 25;
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`check(x[i], 100);
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x[i] /= 5;
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`check(x[i], 20);
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x[i] %= 3;
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`check(x[i], 2);
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x[i] = 'haa;
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x[i] &= 'h33;
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`check(x[i], 'h22);
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x[i] |= 'h11;
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`check(x[i], 'h33);
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x[i] ^= 'h22;
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`check(x[i], 'h11);
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x[i] <<= 3;
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`check(x[i], 'h88);
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x[i] <<<= 1;
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`check(x[i], 'h110);
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x[i] >>= 2;
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`check(x[i], 'h44);
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x[i] >>>= 1;
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`check(x[i], 'h22);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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